NCP81109F Datasheet by ON Semiconductor

0N Semiconductor®

February, 2014 − Rev. P0

1Publication Order Number:

NCP81109F/D

NCP81109F

Product Preview

Single-Phase Voltage

Regulator with SVID

Interface for Computing

Applications

High Switching Frequency, High

Efficiency, Integrated Power MOSFETs

The NCP81109F, a single−phase synchronous buck regulator,

integrates power MOSFETs to provide a high−efficiency and

compact−footprint power management solution for new generation

computing CPUs. The device is able to deliver up to 14 A TDC output

current on an adjustable output with SVID interface. Operating in high

switching frequency up to 1.2 MHz allows employing small size

inductors and capacitors while maintaining high efficiency due to

integrated solution with high performance power MOSFETs.

Current−mode RPM control with feedforward from both input power

supply and output voltage ensures stable operation over wide

operation condition. The NCP81109F is in a QFN48 6 x 6 mm

package.

Features

•Meets Intel® Server Specifications

•5 V to 20 V Input Voltage Range

•1.0 V/1.5 V Fixed Boot Voltage

•Adjustable Output Voltage with SVID Interface

•Integrated Gate Driver and Power MOSFETs

•Up to 14 A TDC Output Current

•500 kHz ~ 1.2 MHz Switching Frequency

•Current−Mode RPM Control

•Programmable SVID Address and ICCMax

•Programmable DVID Feed−Forward to Support Fast DVID

•Feedforward Operation for Input Supply Voltage and Output Voltage

•Output Over−Voltage and Under−Voltage Protections

•External Current Limitation Programming with Inductor Current

Sense

•QFN48, 6 x 6 mm, 0.4 mm Pitch Package

•This is a Pb−Free Device

Typical Applications

•Server Applications

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

Device Package Shipping†

ORDERING INFORMATION

NCP81109FMNTXG QFN48

(Pb−Free)

2500 / Tape &

Reel

QFN48

CASE 485CJ

MARKING

DIAGRAM

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†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

481 NCP81109F

AWLYYWWG

NCP81109F = Specific Device Code

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

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VIN

VRHOT#

47 46

SDIO2

ALERT#

SCLK

GND

VRRDY

VCC

VSP

44 43

VSN

DIFFOUT

41 40

COMP

FREQ

CSREF

38 37

CSSUM

CSCOMP

ILIM

14 1513 17 1816 20 2119 23 2422

IOUT 36

IMAX 35

GND

34TSENSE

33VCCP

VIN

BST

VIN

PGND

VIN

PGND

VIN

PGND

GND

VBOOT

Figure 1. Pin Configuration

(Top View)

VIN

BST

VCCP

ILIM

GND

FREQ

VCC

VRHOT#

PGND

SDIO

ALERT#

SCLK

IMAX

TSENSE

CSREF

CSSUM

CSCOMP

VSN

VRRDY

VIN

+5V VOUT

NCP81109F

VSP

DIFFOUT

IOUT

COMP

VBOOT

Figure 2. Typical Application Circuit

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PWM

Control

SVID Interface

UVLO

VIN

PGND

VCC

GND

BST GH

IOUT

ILIM

CSC

OMP

COMP

DIFF

OUT

VSP

VSN

FREQ

IMAX

SCLK

ALE

RT#

SDIO

VRH

OT#

VCCP

Gate Drive VCCP

Error

Amp

Thermal

Management

Differential

Amplifier

CSR

CSS

Current

Sense

VRRD

Control Logic

Protections

VR Ready

VIN

VSP−VSN

TSENSE

VBOOT

IOUT

IMAX

MUX ADC

Registers

DAC DAC

DAC

Vref

Current Measurement

and Limit

Frequency

VBOOT

Detection

VIN DAC

COMP

OCP

VSP−VSN

DAC

VCS

PWM

DVID

FeedForward

TSEN

IMON

OCP

TSENSE

VBO

1.3V

CSCOMP

CSREF

Figure 3. Functional Block Diagram

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PIN DESCRIPTION

Pin Name Type Description

1 VRHOT# Logic Output VR HOT. Logic low output represents over temperature.

2 SDIO Logic Bidirectional Serial Data IO Port. Data port of SVID interface.

3 ALERT# Logic Output ALERT. Open−drain output. Provides a logic low valid alert signal of SVID interface.

4 SCLK Logic Input Serial Clock. Clock input of SVID interface.

5, 32,

GND Analog Ground Analog Ground. Ground of internal control circuits. Must be connected to the system

ground.

6 VRRDY Logic Output Voltage Regulator Ready. Open−drain output. Provides a logic high valid power good

output signal, indicating the regulator’s output is in regulation window.

11−17,

VIN Power Input Power Supply Input. These pins are the power supply input pins of the device, which are

connected to drain of internal high−side power MOSFET. 22 mF or more ceramic

capacitors must bypass this input to power ground. The capacitors should be placed as

close as possible to these pins.

8 BST Power

Bidirectional

Bootstrap. Provides bootstrap voltage for the high−side gate driver. A 0.1 mF ~ 1 mF

ceramic capacitor is required from this pin to SW (pin 10). A 1 − 2 W resistor may be

employed in series with the BST cap to reduce switching noise and ringing when needed.

9 GH Analog Output Gate of High−Side MOSFET. Directly connected with the gate of the high−side power

MOSFET.

10 SW Power Return Switching Node. Provides a return path for integrated high−side gate driver. It is internally

connected to source of high−side MOSFET.

18,

25−29,

SW Power Output Switch Node. Pins to be connected to an external inductor. These pins are

interconnection between internal high−side MOSFET and low−side MOSFET.

19−24 PGND Power Ground Power Ground. These pins are the power supply ground pins of the device, which are

connected to source of internal low−side power MOSFET. Must be connected to the

system ground.

30 GL Analog Output Gate of Low−Side MOSFET. Directly connected with the gate of the low−side power

MOSFET.

31 VBOOT Analog Input Boot−Up Voltage. A resistor from this pin to ground programs SVID address.

33 VCCP Analog Power Voltage Supply of Gate Driver. Power supply input pin of internal gate driver. A 4.7 mF or

larger ceramic capacitor bypasses this input to ground. This capacitor should be placed as

close as possible to this pin.

34 TSENSE Analog Temperature Sense. An external temperature sense network is connected to this pin.

35 IMAX Analog Input Current Maximum. A resistor from this pin to ground programs IMAX.

36 IOUT Analog Output OUT Current Monitor. Provides output signal representing output current by connecting a

resistor from this pin to ground. Shorting this pin to ground disables IMON function.

37 ILIM Analog Output Limit of Current. A resistor from this pin to CSCOMP programs over−current threshold

with inductor current sense.

38 CSCOMP Analog Output Current Sense COMP. Output pin of current sense amplifier.

39 CSSUM Analog Input Current Sense SUM. Inverting input of current sense amplifier.

40 CSREF Analog Input Current Sense Reference. Non−Inverting input of current sense amplifier.

41 FREQ Analog Input Frequency. A resistor from this pin to ground programs switching frequency.

42 COMP Analog Compensation. Output pin of error amplifier.

43 FB Analog Input Feedback. Inverting input to error amplifier.

44 DIFFOUT Analog Output Differential Amplifier Output. Output pin of differential voltage sense amplifier.

45 VSN Analog Input Voltage Sense Negative Input. Inverting input of differential voltage sense amplifier. It is

also used for DVID feed forward function with an external resistor.

46 VSP Analog Input Voltage Sense Positive Input. Non−inverting input of differential voltage sense amplifier.

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PIN DESCRIPTION

Pin DescriptionTypeName

47 VCC Analog Power Voltage Supply of Controller. Power supply input pin of control circuits. A 1 mF or larger

ceramic capacitor bypasses this input to ground. This capacitor should be placed as close

as possible to this pin.

48 EN Logic Input Enable. Logic high enables the device and logic low makes the device in standby mode.

MAXIMUM RATINGS

Rating Symbol

Value

Unit

Min Max

Power Supply Voltage to PGND VVIN 30 V

Switch Node to PGND VSW 30 V

Analog Supply Voltage to GND VCC, VCCP −0.3 6.5 V

BST to PGND BST_PGND −0.3 33

38 (<50 ns)

BST to SW BST_SW −0.3 6.5 V

GH to SW GH −0.3

−2 (<200 ns)

BST+0.3 V

GL to GND GL −0.3

−2 (<200 ns)

VCCP+0.3 V

VSN to GND VSN −0.3 0.3 V

IOUT IOUT −0.3 2.5 V

PGND to GND PGND −0.3 0.3 V

Other Pins −0.3 VCC+0.3 V

Latch up Current: (Note 1)

All pins, except digital pins

Digital pins

ILU −100

−10

100

Operating Junction Temperature Range TJ−10 125 °C

Operating Ambient Temperature Range TA−10 100 °C

Storage Temperature Range TSTG −40 150 °C

Thermal Resistance Junction to Board (Note 2) RθJB 8.2 °C/W

Thermal Resistance Junction to Ambient (Note 2) RθJA 21.8 °C/W

Power Dissipation at TA = 25°C (Note 3) PD4.59 W

Moisture Sensitivity Level (Note 4) MSL 3 −

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Latch up Current per JEDEC standard: JESD78 class II.

2. The thermal resistance values are dependent of the internal losses split between devices and the PCB heat dissipation. This data is based

on a typical operation condition with a 4−layer FR−4 PCB board, which has two, 1−ounce copper internal power and ground planes and

2−ounce copper traces on top and bottom layers with approximately 80% copper coverage. No airflow and no heat sink applied (reference

EIA/JEDEC 51.7). It also does not account for other heat sources that may be present on the PCB next to the device in question (such as

inductors, resistors etc.)

3. The maximum power dissipation (PD) is dependent on input voltage, output voltage, output current, external components selected, and PCB

layout. The reference data is obtained based on TJMAX = 125°C and RθJA = 21.8°C/W.

4. Moisture Sensitivity Level (MSL): 3 per IPC/JEDEC standard: J−STD−020D.1.

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ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, VOUT = 1.0 V, typical values are referenced to TJ = 25°C, Min

and Max values are referenced to TJ from −10°C to 100°C. unless otherwise noted.)

Characteristics Test Conditions Symbol Min Typ Max Unit

SUPPLY VOLTAGE

Supply Voltage VIN Range (Note 5) VIN 12 V

Supply Voltage VCC Range (Note 5) VCC 4.75 5 5.25 V

Supply Voltage VCCP Range (Note 5) VCCP 4.75 5 5.25 V

SUPPLY VOLTAGE MONITOR

VIN UVLO Falling Threshold VINUV−3.0 3.25 3.5 V

Hysteresis VINHYS 650 −mV

VCC UVLO Falling Threshold VCCUV−3.8 4.08 −V

Rising Threshold VCCUV+ −4.34 4.5 V

Hysteresis VCCHYS −260 −mV

SUPPLY CURRENT

VIN Quiescent Supply Current

(Power MOSFETs)

EN high, no load, PS0,1,2 Modes

EN high, no load, PS3 Mode

EN high, PS4 Mode (Note 6)

IQ−

−

1.5

−

VIN Shutdown Current EN low (Note 6) ISD − − 1mA

VCC Quiescent Supply Current

(Controller)

EN high, no load, PS0,1,2 Modes

EN high, no load, PS3 Mode

EN high, PS4 Mode (Note 6)

IQCC −

−

8.0

7.5

170

194

VCC Shutdown Current EN low (Note 6) ISDCC − − 90 mA

VCCP Quiescent Supply Current

(Gate Driver)

EN high, no load, PS0,1,2 Modes

EN high, no load, PS3 Mode

EN high, PS4 Mode

IQCCP −

−

0.7

−

1.25

VCCP Shutdown Current EN low ISDCCP − − 2mA

OUTPUT VOLTAGE

Output Voltage Range (Note 5) VOUT 0−2.3 V

REGULATION ACCURACY

System Voltage Accuracy 0.5 V < DAC < 1.52 V

0.25 V < DAC < 0.495 V

−8

−10

DVID

Fast Slew Rate Default FSR 14 mV/ms

Soft Start Slew Rate SSSR FSR/4 mV/ms

Slow Slew Rate SSR FSR/2

FSR/4

(default)

FSR/8

FSR/16

mV/ms

DIFFERENTIAL VOLTAGE−SENSE AMPLIFIER

DC Gain VSP−VSN = 0.5 V to 2.3 V GAIN_DVA 1.0 V/V

−3 dB Gain Bandwidth CL = 20 pF to GND, RL = 10 kW to

GND (Note 5)

BW_DVA 10 MHz

VSP Input Voltage Range (Note 5) VSP −0.3 −3.0 V

VSN Input Voltage Range (Note 5) VSN −0.3 −0.3 V

Input Bias Current VSP,CSREF = 1.3 V IVSP

IVSN

−15

−100

100

5. Guaranteed by design, not tested in production.

6. TJ = 25°C.

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ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, VOUT = 1.0 V, typical values are referenced to TJ = 25°C, Min

and Max values are referenced to TJ from −10°C to 100°C. unless otherwise noted.)

Characteristics UnitMaxTypMinSymbolTest Conditions

DIFFERENTIAL CURRENT−SENSE AMPLIFIER

DC Gain (Note 5) GAIN_DCA 80 dB

−3dB Gain Bandwidth CL = 20 pF to GND, RL = 10 kW to

GND (Note 5)

BW_DCA 10 MHz

Input Offset Voltage VOS_CS −300 −300 mV

Input Bias Current CSSUM = CSREF = 1.2 V ICSSUM

ICSREF

−7.5

−10

7.5

ERROR AMPLIFIER

DC Gain CL = 20 pF to GND, RL = 10 kW to

GND (Note 5)

GAIN_EA 80 dB

Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 kW to

GND (Note 5)

BW_EA 20 MHz

Slew Rate nVin = 100 mV, G = −10 V/V,

nVout = 1.5 V – 2.5 V,

CL = 20 pF to GND, RL = 10 kW to

GND (Note 5)

SR_EA 25 V/ms

Output Voltage Swing Isource_EA = 2 mA Vmax_EA 3.5 − − V

Isink_EA = 2 mA Vmin_EA − − 1

FB Voltage VFB 1.3 V

Input Bias Current VFB = 1.3 V IFB −1.5 1.5 mA

SWITCHING FREQUENCY

Normal Operation Frequency

(Programmed by a resistor at FREQ

pin)

(Note 5) FSW 500 1200 kHz

FREQ Output Voltage VFREQ 1.95 2.0 2.05 V

CONTROL LOGIC

ENABLE Input High Voltage VEN_H 0.8 − − V

ENABLE Input Low Voltage VEN_L − − 0.3 V

ENABLE Input Hysteresis VEN_HYS −300 −mV

ENABLE Input Bias Current IEN_BIAS −1.0 mA

SCLK, SDIO

Input High Voltage VIH 0.65 V

Input Low Voltage VIL 0.45 V

Input Threshold Hysteresis VHYS 50 mV

Output High Voltage (Note 5) VOH 1.05 V

Output Low Voltage SDIO VOL 0.3 V

Buffer On Resistance (data line,

ALERT#, and VR_HOT#)

RON 3.0 13 W

Input Leakage Current Pin voltage between 0 and 1.05 V −100 100 mA

Input Capacitance Die capacitance only (Note 5) 4.0 pF

VR Clock to Data Delay Time between SCLK rising edge and

valid SDIO level (Note 5)

Tco 4 8.3 ns

Setup Time Time before SCLK falling (sampling)

edge that SDIO level must be valid

(Note 5)

Tsu 7 ns

5. Guaranteed by design, not tested in production.

6. TJ = 25°C.

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ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, VOUT = 1.0 V, typical values are referenced to TJ = 25°C, Min

and Max values are referenced to TJ from −10°C to 100°C. unless otherwise noted.)

Characteristics UnitMaxTypMinSymbolTest Conditions

SCLK, SDIO

Hold Time Time after SCLK falling edge that the

SDIO level remains valid (Note 5)

Thld 14 ns

ALERT#

Output Low Voltage I_ ALERT # = −4 mA − − 0.3 V

Output Leakage Current High Impedance State, ALERT # =

3.3 V

−1.0 −1.0 mA

VR_HOT#

Output Low Voltage I_VRHOT# = −4 mA − − 0.3 V

Output Leakage Current High Impedance State, VRHOT# =

3.3 V

−1.0 −1.0 mA

TSENSE

Alert# Assert Threshold 491 mV

Alert# De−assert Threshold 513 mV

VR_HOT# Assert Threshold 472 mV

VR_HOT# De−assert Threshold 494 mV

TSENSE Bias Current VTSENSE = 0.4 V 115 120 125 mA

VBOOT

Sensing Current VVBOOT = GND 10 mA

IMAX

Sensing Current VIMAX = GND 10 mA

ADC

Voltage Range 0 2.0 V

Total Unadjusted Error (TUE) −1 1 %

Differential Nonlinearity (DNL) 8−bit 1 LSB

Power Supply Sensitivity ±1 %

Conversion Time 30 ms

Round Robin 90 ms

VR_READY (VRRDY Output)

Rise Time External 1 kW pull−up to 3.3 V,

CTOT = 45 pF, DVo = 10% to 90%

100 ns

Fall Time External 1 kW pull−up to 3.3 V,

CTOT = 45 pF, DVo = 90% to 10%

10 ns

Output Voltage at Power−Up Pulled up to 5 V via 2 kW− − 1.0 V

VR_READY Delay (Rising) DAC = Target to VR_READY 50 ms

VR_READY Delay (Falling) From OCP or OVP 5ms

VRRDY Pin Low Voltage Voltage at VRRDY pin with 4 mA sink

current

VPG_L − − 0.3 V

VRRDY Pin Leakage Current VRRDY = 5 V PG_LK −1.0 −1.0 mA

OVER VOLTAGE PROTECTION

Absolute Over Voltage Threshold

During Soft−Start

2.8 2.9 3.0 V

5. Guaranteed by design, not tested in production.

6. TJ = 25°C.

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ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, VOUT = 1.0 V, typical values are referenced to TJ = 25°C, Min

and Max values are referenced to TJ from −10°C to 100°C. unless otherwise noted.)

Characteristics UnitMaxTypMinSymbolTest Conditions

OVER VOLTAGE PROTECTION

Over Voltage Threshold Above DAC VSP rising 350 400 425 mV

Over Voltage Delay VSP rising to GH low 50 ns

UNDER VOLTAGE PROTECTION

Under Voltage Threshold Below DAC VSP falling 250 300 350 mV

Under−voltage Delay 5ms

OVER CURRENT PROTECTION

ILIM Threshold Current

(OCP shutdown after 50 ms delay)

ILIMTH_SLOW 9.0 10.0 11.0

ILIM Threshold Current

(immediate OCP shutdown)

ILIMTH_FAST 13.5 15.0 16.5

IOUT OUTPUT

Current Gain (IOUTCURRENT) / (ILIMCURRENT);

RILIM = 20 kW; RIOUT = 5.0 kW;

DAC = 0.8 V, 1.25 V, 1.52 V

9.5 10 10.5 A/A

Input Referred Offset Voltage ILIM − CSREF −2.0 −2.0 mV

Output Source Current ILIM sink current = 80 mA800 mA

HIGH−SIDE MOSFET

Drain−to−Source ON Resistance VGS = 4.5 V, ID = 10 A RON_H −8.0 −mW

LOW−SIDE MOSFET

Drain−to−Source ON Resistance VGS = 4.5 V, ID = 10 A RON_L −4.0 −mW

HIGH−SIDE GATE DRIVE

Pull−High Drive ON Resistance VBST – VSW = 5 V RDRV_HH −1.2 2.8 W

Pull−Low Drive ON Resistance VBST – VSW = 5 V RDRV_HL −0.8 2.0 W

GH Propagation Delay Time From GL falling to GH rising TGH_d 15 ns

LOW−SIDE GATE DRIVE

Pull−High Drive ON Resistance VCCP – VPGND = 5 V RDRV_LH −0.9 2.8 W

Pull−Low Drive ON Resistance VCCP – VPGND = 5 V RDRV_LL −0.4 1.25 W

GL Propagation Delay Time From GH falling to GL rising TGL_d 10 ns

SW to PGND RESISTANCE

SW to PGND Pull−Down Resistance (Note 5) RSW −1.88 −kW

BOOTSTRAP RECTIFIER SWITCH

On Resistance EN = L or EN = H and DRVL = H Ron_BST 5 13 20 W

5. Guaranteed by design, not tested in production.

6. TJ = 25°C.

)) (( VCC VRI 2.6 EN VR RDY SVID ALERT svc ><><><><><><><><><><><>o<><>o<><><><><><>

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VTH VTH

1.0 V

TGH _d

TGL_d

TGH_r

TGH_f

TGL_r

GH to SW

TGL_f

NOTE: Timing is referenced to the 90% and 10% points, unless otherwise noted.

Figure 4. Timing Diagram of Gate Drivers

Figure 5. Timing Diagram of Start Up

Table 1. START−UP AND ENABLE TIMINGS

Symbol Description

Values

Note

Min Typ Max

TA Non−zero Vboot Case: start of Vboot ramp

Zero Vboot Case: Controller ready accept

SVID command

2.5 ms Complete all internal analog and digital

configurations and reset protocols dur-

ing TA. May be disclosed to CPU

through register 2Dh.

TB Vboot ramp time Depends on Slew rate When Vboot > 0 V, the VR is to slew at

the default Slow rate of FAST/4

TC Completion of Vboot ramp or initial SetVID

ramp to assertion of associated VR_READY

0 ms6 ms

aw \ /\ /

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SCLK

SDIO

TCO_CPU tSU thld TCO_CPU

VR latch

CPU

send

Tco_CPU = clock to data delay in CPU

tsu =0.5*T−Tco_CPU

thld =0.5*T +Tco_CPU

CPU Driving, Single Data Rate

SCLK

SDIO

TCO_VR tSU thld

CPU latch

send

Tco_VR = clock to data delay in VR

tsu =T−2*Tfly −Tco_VR

thld =2*Tfly +Tco_VR

Tfly propagation time on Serial VID bus

VR Driving, Single Data Rate

Figure 6. Timing Diagram of SVID

Table 2. STATE TRUTH TABLE

STATE VR_RDY Pin Error AMP Comp Pin OVP & UVP Method of Reset

POR

0 < VCC < UVLO

N/A N/A N/A

Disabled

EN < threshold

UVLO > threshold

Low Low Disabled

Start up Delay & Calibration

EN > threshold

UVLO > threshold

Low Low Disabled

Soft Start

EN > threshold

UVLO > threshold

Low Operational Active / No latch

Normal Operation

EN > threshold

UVLO > threshold

High Operational Active / Latching N/A

Over Voltage Low N/A DAC + 400 mV

Over Current Low Operational Last DAC Code

VID Code = 00h Low: if Reg34h:bit0 = 0;

High:if Reg34h:bit0 = 1

Clamped at 0.9 V Disabled

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Table 3. VR12 VID CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage (V) HEX

0 0 0 0 0 0 0 0 OFF 00

0 0 0 0 0 0 0 1 0.25000 01

0 0 0 0 0 0 1 0 0.25500 02

0 0 0 0 0 0 1 1 0.26000 03

0 0 0 0 0 1 0 0 0.26500 04

0 0 0 0 0 1 0 1 0.27000 05

0 0 0 0 0 1 1 0 0.27500 06

0 0 0 0 0 1 1 1 0.28000 07

0 0 0 0 1 0 0 0 0.28500 08

0 0 0 0 1 0 0 1 0.29000 09

0 0 0 0 1 0 1 0 0.29500 0A

0 0 0 0 1 0 1 1 0.30000 0B

0 0 0 0 1 1 0 0 0.30500 0C

0 0 0 0 1 1 0 1 0.31000 0D

0 0 0 0 1 1 1 0 0.31500 0E

0 0 0 0 1 1 1 1 0.32000 0F

0 0 0 1 0 0 0 0 0.32500 10

0 0 0 1 0 0 0 1 0.33000 11

0 0 0 1 0 0 1 0 0.33500 12

0 0 0 1 0 0 1 1 0.34000 13

0 0 0 1 0 1 0 0 0.34500 14

0 0 0 1 0 1 0 1 0.35000 15

0 0 0 1 0 1 1 0 0.35500 16

0 0 0 1 0 1 1 1 0.36000 17

0 0 0 1 1 0 0 0 0.36500 18

0 0 0 1 1 0 0 1 0.37000 19

0 0 0 1 1 0 1 0 0.37500 1A

0 0 0 1 1 0 1 1 0.38000 1B

0 0 0 1 1 1 0 0 0.38500 1C

0 0 0 1 1 1 0 1 0.39000 1D

0 0 0 1 1 1 1 0 0.39500 1E

0 0 0 1 1 1 1 1 0.40000 1F

0 0 1 0 0 0 0 0 0.40500 20

0 0 1 0 0 0 0 1 0.41000 21

0 0 1 0 0 0 1 0 0.41500 22

0 0 1 0 0 0 1 1 0.42000 23

0 0 1 0 0 1 0 0 0.42500 24

0 0 1 0 0 1 0 1 0.43000 25

0 0 1 0 0 1 1 0 0.43500 26

0 0 1 0 0 1 1 1 0.44000 27

0 0 1 0 1 0 0 0 0.44500 28

0 0 1 0 1 0 0 1 0.45000 29

0 0 1 0 1 0 1 0 0.45500 2A

0 0 1 0 1 0 1 1 0.46000 2B

0 0 1 0 1 1 0 0 0.46500 2C

0 0 1 0 1 1 0 1 0.47000 2D

0 0 1 0 1 1 1 0 0.47500 2E

0 0 1 0 1 1 1 1 0.48000 2F

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Table 3. VR12 VID CODES

VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6

0 0 1 1 0 0 0 0 0.48500 30

0 0 1 1 0 0 0 1 0.49000 31

0 0 1 1 0 0 1 0 0.49500 32

0 0 1 1 0 0 1 1 0.50000 33

0 0 1 1 0 1 0 0 0.50500 34

0 0 1 1 0 1 0 1 0.51000 35

0 0 1 1 0 1 1 0 0.51500 36

0 0 1 1 0 1 1 1 0.52000 37

0 0 1 1 1 0 0 0 0.52500 38

0 0 1 1 1 0 0 1 0.53000 39

0 0 1 1 1 0 1 0 0.53500 3A

0 0 1 1 1 0 1 1 0.54000 3B

0 0 1 1 1 1 0 0 0.54500 3C

0 0 1 1 1 1 0 1 0.55000 3D

0 0 1 1 1 1 1 0 0.55500 3E

0 0 1 1 1 1 1 1 0.56000 3F

0 1 0 0 0 0 0 0 0.56500 40

0 1 0 0 0 0 0 1 0.57000 41

0 1 0 0 0 0 1 0 0.57500 42

0 1 0 0 0 0 1 1 0.58000 43

0 1 0 0 0 1 0 0 0.58500 44

0 1 0 0 0 1 0 1 0.59000 45

0 1 0 0 0 1 1 0 0.59500 46

0 1 0 0 0 1 1 1 0.60000 47

0 1 0 0 1 0 0 0 0.60500 48

0 1 0 0 1 0 0 1 0.61000 49

0 1 0 0 1 0 1 0 0.61500 4A

0 1 0 0 1 0 1 1 0.62000 4B

0 1 0 0 1 1 0 0 0.62500 4C

0 1 0 0 1 1 0 1 0.63000 4D

0 1 0 0 1 1 1 0 0.63500 4E

0 1 0 0 1 1 1 1 0.64000 4F

0 1 0 1 0 0 0 0 0.64500 50

0 1 0 1 0 0 0 1 0.65000 51

0 1 0 1 0 0 1 0 0.65500 52

0 1 0 1 0 0 1 1 0.66000 53

0 1 0 1 0 1 0 0 0.66500 54

0 1 0 1 0 1 0 1 0.67000 55

0 1 0 1 0 1 1 0 0.67500 56

0 1 0 1 0 1 1 1 0.68000 57

0 1 0 1 1 0 0 0 0.68500 58

0 1 0 1 1 0 0 1 0.69000 59

0 1 0 1 1 0 1 0 0.69500 5A

0 1 0 1 1 0 1 1 0.70000 5B

0 1 0 1 1 1 0 0 0.70500 5C

0 1 0 1 1 1 0 1 0.71000 5D

0 1 0 1 1 1 1 0 0.71500 5E

0 1 0 1 1 1 1 1 0.72000 5F

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Table 3. VR12 VID CODES

VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6

0 1 1 0 0 0 0 0 0.72500 60

0 1 1 0 0 0 0 1 0.73000 61

0 1 1 0 0 0 1 0 0.73500 62

0 1 1 0 0 0 1 1 0.74000 63

0 1 1 0 0 1 0 0 0.74500 64

0 1 1 0 0 1 0 1 0.75000 65

0 1 1 0 0 1 1 0 0.75500 66

0 1 1 0 0 1 1 1 0.76000 67

0 1 1 0 1 0 0 0 0.76500 68

0 1 1 0 1 0 0 1 0.77000 69

0 1 1 0 1 0 1 0 0.77500 6A

0 1 1 0 1 0 1 1 0.78000 6B

0 1 1 0 1 1 0 0 0.78500 6C

0 1 1 0 1 1 0 1 0.79000 6D

0 1 1 0 1 1 1 0 0.79500 6E

0 1 1 0 1 1 1 1 0.80000 6F

0 1 1 1 0 0 0 0 0.80500 70

0 1 1 1 0 0 0 1 0.81000 71

0 1 1 1 0 0 1 0 0.81500 72

0 1 1 1 0 0 1 1 0.82000 73

0 1 1 1 0 1 0 0 0.82500 74

0 1 1 1 0 1 0 1 0.83000 75

0 1 1 1 0 1 1 0 0.83500 76

0 1 1 1 0 1 1 1 0.84000 77

0 1 1 1 1 0 0 0 0.84500 78

0 1 1 1 1 0 0 1 0.85000 79

0 1 1 1 1 0 1 0 0.85500 7A

0 1 1 1 1 0 1 1 0.86000 7B

0 1 1 1 1 1 0 0 0.86500 7C

0 1 1 1 1 1 0 1 0.87000 7D

0 1 1 1 1 1 1 0 0.87500 7E

0 1 1 1 1 1 1 1 0.88000 7F

1 0 0 0 0 0 0 0 0.88500 80

1 0 0 0 0 0 0 1 0.89000 81

1 0 0 0 0 0 1 0 0.89500 82

1 0 0 0 0 0 1 1 0.90000 83

1 0 0 0 0 1 0 0 0.90500 84

1 0 0 0 0 1 0 1 0.91000 85

1 0 0 0 0 1 1 0 0.91500 86

1 0 0 0 0 1 1 1 0.92000 87

1 0 0 0 1 0 0 0 0.92500 88

1 0 0 0 1 0 0 1 0.93000 89

1 0 0 0 1 0 1 0 0.93500 8A

1 0 0 0 1 0 1 1 0.94000 8B

1 0 0 0 1 1 0 0 0.94500 8C

1 0 0 0 1 1 0 1 0.95000 8D

1 0 0 0 1 1 1 0 0.95500 8E

1 0 0 0 1 1 1 1 0.96000 8F

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Table 3. VR12 VID CODES

VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6

1 0 0 1 0 0 0 0 0.96500 90

1 0 0 1 0 0 0 1 0.97000 91

1 0 0 1 0 0 1 0 0.97500 92

1 0 0 1 0 0 1 1 0.98000 93

1 0 0 1 0 1 0 0 0.98500 94

1 0 0 1 0 1 0 1 0.99000 95

1 0 0 1 0 1 1 0 0.99500 96

1 0 0 1 0 1 1 1 1.00000 97

1 0 0 1 1 0 0 0 1.00500 98

1 0 0 1 1 0 0 1 1.01000 99

1 0 0 1 1 0 1 0 1.01500 9A

1 0 0 1 1 0 1 1 1.02000 9B

1 0 0 1 1 1 0 0 1.02500 9C

1 0 0 1 1 1 0 1 1.03000 9D

1 0 0 1 1 1 1 0 1.03500 9E

1 0 0 1 1 1 1 1 1.04000 9F

1 0 1 0 0 0 0 0 1.04500 A0

1 0 1 0 0 0 0 1 1.05000 A1

1 0 1 0 0 0 1 0 1.05500 A2

1 0 1 0 0 0 1 1 1.06000 A3

1 0 1 0 0 1 0 0 1.06500 A4

1 0 1 0 0 1 0 1 1.07000 A5

1 0 1 0 0 1 1 0 1.07500 A6

1 0 1 0 0 1 1 1 1.08000 A7

1 0 1 0 1 0 0 0 1.08500 A8

1 0 1 0 1 0 0 1 1.09000 A9

1 0 1 0 1 0 1 0 1.09500 AA

1 0 1 0 1 0 1 1 1.10000 AB

1 0 1 0 1 1 0 0 1.10500 AC

1 0 1 0 1 1 0 1 1.11000 AD

1 0 1 0 1 1 1 0 1.11500 AE

1 0 1 0 1 1 1 1 1.12000 AF

1 0 1 1 0 0 0 0 1.12500 B0

1 0 1 1 0 0 0 1 1.13000 B1

1 0 1 1 0 0 1 0 1.13500 B2

1 0 1 1 0 0 1 1 1.14000 B3

1 0 1 1 0 1 0 0 1.14500 B4

1 0 1 1 0 1 0 1 1.15000 B5

1 0 1 1 0 1 1 0 1.15500 B6

1 0 1 1 0 1 1 1 1.16000 B7

1 0 1 1 1 0 0 0 1.16500 B8

1 0 1 1 1 0 0 1 1.17000 B9

1 0 1 1 1 0 1 0 1.17500 BA

1 0 1 1 1 0 1 1 1.18000 BB

1 0 1 1 1 1 0 0 1.18500 BC

1 0 1 1 1 1 0 1 1.19000 BD

1 0 1 1 1 1 1 0 1.19500 BE

1 0 1 1 1 1 1 1 1.20000 BF

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Table 3. VR12 VID CODES

VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6

1 1 0 0 0 0 0 0 1.20500 C0

1 1 0 0 0 0 0 1 1.21000 C1

1 1 0 0 0 0 1 0 1.21500 C2

1 1 0 0 0 0 1 1 1.22000 C3

1 1 0 0 0 1 0 0 1.22500 C4

1 1 0 0 0 1 0 1 1.23000 C5

1 1 0 0 0 1 1 0 1.23500 C6

1 1 0 0 0 1 1 1 1.24000 C7

1 1 0 0 1 0 0 0 1.24500 C8

1 1 0 0 1 0 0 1 1.25000 C9

1 1 0 0 1 0 1 0 1.25500 CA

1 1 0 0 1 0 1 1 1.26000 CB

1 1 0 0 1 1 0 0 1.26500 CC

1 1 0 0 1 1 0 1 1.27000 CD

1 1 0 0 1 1 1 0 1.27500 CE

1 1 0 0 1 1 1 1 1.28000 CF

1 1 0 1 0 0 0 0 1.28500 D0

1 1 0 1 0 0 0 1 1.29000 D1

1 1 0 1 0 0 1 0 1.29500 D2

1 1 0 1 0 0 1 1 1.30000 D3

1 1 0 1 0 1 0 0 1.30500 D4

1 1 0 1 0 1 0 1 1.31000 D5

1 1 0 1 0 1 1 0 1.31500 D6

1 1 0 1 0 1 1 1 1.32000 D7

1 1 0 1 1 0 0 0 1.32500 D8

1 1 0 1 1 0 0 1 1.33000 D9

1 1 0 1 1 0 1 0 1.33500 DA

1 1 0 1 1 0 1 1 1.34000 DB

1 1 0 1 1 1 0 0 1.34500 DC

1 1 0 1 1 1 0 1 1.35000 DD

1 1 0 1 1 1 1 0 1.35500 DE

1 1 0 1 1 1 1 1 1.36000 DF

1 1 1 0 0 0 0 0 1.36500 E0

1 1 1 0 0 0 0 1 1.37000 E1

1 1 1 0 0 0 1 0 1.37500 E2

1 1 1 0 0 0 1 1 1.38000 E3

1 1 1 0 0 1 0 0 1.38500 E4

1 1 1 0 0 1 0 1 1.39000 E5

1 1 1 0 0 1 1 0 1.39500 E6

1 1 1 0 0 1 1 1 1.40000 E7

1 1 1 0 1 0 0 0 1.40500 E8

1 1 1 0 1 0 0 1 1.41000 E9

1 1 1 0 1 0 1 0 1.41500 EA

1 1 1 0 1 0 1 1 1.42000 EB

1 1 1 0 1 1 0 0 1.42500 EC

1 1 1 0 1 1 0 1 1.43000 ED

1 1 1 0 1 1 1 0 1.43500 EE

1 1 1 0 1 1 1 1 1.44000 EF

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Table 3. VR12 VID CODES

VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6

1 1 1 1 0 0 0 0 1.44500 F0

1 1 1 1 0 0 0 1 1.45000 F1

1 1 1 1 0 0 1 0 1.45500 F2

1 1 1 1 0 0 1 1 1.46000 F3

1 1 1 1 0 1 0 0 1.46500 F4

1 1 1 1 0 1 0 1 1.47000 F5

1 1 1 1 0 1 1 0 1.47500 F6

1 1 1 1 0 1 1 1 1.48000 F7

1 1 1 1 1 0 0 0 1.48500 F8

1 1 1 1 1 0 0 1 1.49000 F9

1 1 1 1 1 0 1 0 1.49500 FA

1 1 1 1 1 0 1 1 1.50000 FB

1 1 1 1 1 1 0 0 1.50500 FC

1 1 1 1 1 1 0 1 1.51000 FD

1 1 1 1 1 1 1 0 1.51500 FE

1 1 1 1 1 1 1 1 1.52000 FF

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Table 4. SUPPORTED REGISTERS

Index Name Description Access Default

00h Vendor ID Uniquely identifies the VR vendor. The vendor ID assigned by Intel to

ON Semiconductor is 0x1Ah

R 1Ah

01h Product ID Uniquely identifies the VR product. The VR vendor assigns this number. R 19h

02h Product Revision Uniquely identifies the revision or stepping of the VR control IC. The VR vendor

assigns this data.

R 00h

03h Date code ID R 00h

05h Protocol ID Identifies the SVID Protocol the controller supports R 01h

06h Capability Informs the Master of the controller’s Capabilities, 1 = supported, 0 = not supported

Bit 7 = Iout_format. Bit 7 = 0 when 1A = 1LSB of Reg 15h. Bit 7 = 1 when Reg 15

FFh = Icc_Max. Default = 1

Bit 6 = ADC Measurement of Temp Supported = 1

Bit 5 = ADC Measurement of Pin Supported = 0

Bit 4 = ADC Measurement of Vin Supported = 0

Bit 3 = ADC Measurement of Iin Supported = 0

Bit 2 = ADC Measurement of Pout Supported = 1

Bit 1 = ADC Measurement of Vout Supported = 1

Bit 0 = ADC Measurement of Iout Supported = 1

R D7h

10h Status_1 Data register read after ALERT# signal is asserted. Conveying the status of the VR. R 00h

11h Status_2 Data register showing optional status_2 data. R 00h

12h Temp zone Data register showing temperature zones the system is operating in R 00h

15h I_out 8 bit binary word ADC of current. This register reads 0xFF when the IOUT(A) pin

voltage is 2 V. The IOUT(A) voltage should be scaled with an external resister to

ground such that a load equal to Icc_Max generates a 2 V signal.

R 01h

16h V_out 8 bit binary ADC of output voltage between VSP and VSN. LSB size is 8 mV R 01h

17h VR_Temp 8 bit binary word ADC of voltage. Binary format in deg C, IE 100C = 64h. A value of

00h indicates this function is not supported

R 01h

18h P_out 8 bit binary word representative of output power. The output voltage is multiplied by

the output current value and the result is stored in this register. A value of 00h in-

dicates this function is not supported

R 01h

1Ch Status 2 Last

read

When the status 2 register is read its contents are copied into this register. The

format is the same as the Status 2 Register.

R 00h

21h Icc_Max Data register containing the Icc_Max. The value is measured on the ICCMAX pin

on power up and placed in this register. From that point on the register is read only.

R 00h

22h Temp_Max Data register containing the max temperature and the level VR_hot asserts. This

value defaults to 100°C and programmable over the SVID Interface

R/W 64h

24h SR_fast Slew Rate for SetVID_fast commands. Binary format in mV/ms. R 32h

25h SR_slow Slew Rate for SetVID_slow commands. It is 4X slower than the SR_fast rate. Bin-

ary format in mV/ms

R 0Ch

26h Vboot The NCP81109F ramps to Vboot and holds at Vboot until it receives a new SVID

SetVID command to move to a different voltage. Default value = 0 V.

R 00h

2Ah SR_Slow

selector

Fast_SR/2

Fast_SR/4: default

Fast_SR/8

Fast_SR/16

R/W 02h

2Bh PS4 exit latency Reflects the latency of exiting PS4 state. The exit latency is defined as the time

duration, in ms, from the ACK of the SETVID Slow/Fast command to the output

voltage beginning to ramp

R 00h

2Ch PS3 exit latency Reflects the latency of exiting PS3 state. The exit latency is defined as the time

duration, in ms, from the ACK of the SETVID/SetPS command until the controller is

capable of supplying max current of the command PS state.

R 00h

2Dh EN to Ready for

SVID command

(TA)

Reflects the latency from enable assertion to the VR controller being ready to ac-

cept SVID commands.

R 00h

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Table 4. SUPPORTED REGISTERS

Index DefaultAccessDescriptionName

30h Vout_Max Programmed by master and sets the maximum VID the VR will support. If a higher

VID code is received, the VR should respond with “not supported” acknowledge.

VR 12 VID format.

RW B5h

31h VID setting Data register containing currently programmed VID voltage. VID data format. RW 00h

32h Pwr State Register containing the current programmed power state. RW 00h

33h Offset Sets offset in VID steps added to the VID setting for voltage margining. Bit 7 is sign

bit, 0 = positive margin, 1 = negative margin. Remaining 7 BITS are # VID steps

for margin 2s complement.

00h = no margin

01h = +1 VID step

02h = +2 VID steps

FFh = −1 VID step

FEh = −2 VID steps.

RW 00h

34h MultiVR Config

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DETAILED DESCRIPTION

General

The NCP81109F, a single−phase synchronous buck

regulator, integrates power MOSFETs to provide a

high−efficiency and compact−footprint power management

solution for new generation computing CPUs. The device is

able to deliver up to 14 A TDC output current on an

adjustable output with SVID interface. Operating in high

switching frequency up to 1.2 MHz allows employing small

size inductors and capacitors while maintaining high

efficiency due to integrated solution with high performance

power MOSFETs. Current−mode RPM control with

feedforward from both input power supply and output

voltage ensures stable operation over wide operation

condition.

Operation Modes

The NCP81109F implements PS0, PS1, PS2, PS3, and

PS4 power operation modes as shown in Table 5.

Table 5. POWER STATUS AND OPERATION MODES

Power Status Operation Mode

PS0 Forced CCM mode – normal mode

PS1 Forced CCM mode – low power mode

PS2 Auto CCM/DCM mode – very low power mode

PS3 Auto CCM/DCM mode – ultra low power mode

PS4 Vout = 0, SVID active only

Current−Mode RPM Operation

The NCP81109F operates with the current−mode

Ramp−Pulse−Modulation (RPM) scheme in PS0/1/2/3

operation modes. In forced CCM mode, the inductor current

is always continuous and the device operates in quasi−fixed

switching frequency, which has a typical value programmed

by users through a resistor at pin FREQ. In auto CCM/DCM

mode, the inductor current is continuous and the device

operates in quasi−fixed switching frequency in medium and

heavy load range, while the inductor current becomes

discontinuous and the device automatically operates in PFM

mode with an adaptive fixed on time and variable switching

frequency in light load range.

Serial VID interface (SVID)

The NCP81109F supports Intel serial VID interface. It

communicates with the microprocessor through three wires

(SCLK, SDIO, ALERT#). SCLK, SDIO and ALERT#

should be pulled high to CPU I/O voltage VTT (which is

typically 1.0 to 1.1 V) using 55 W Resistors. The SVID bus

will operate at a max frequency of 43 MHz. For

NCP81109F, VID code change rate is controlled by the

SVID interface with three options as shown in Table 6. All

the supported registers are shown in Table 4.

Table 6. REGISTERS FOR VID CODE CHANGE RATE

Option SVID Command Code Feature

(Indicating the slew rate of VID code change)

SetVID_Fast 01h selectable slew rate 24h

SetVID_Slow 02h Fast_SR/2

Fast_SR/4: default

Fast_SR/8

Fast_SR/16

25h

SetVID_Decay 03h No control, VID code down N/A

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Start Up Sequence

A timing diagram of start−up sequence is shown in

Figure 5, and timing parameters are shown in Table 1.

Boot Voltage and SVID Address

Table 7 shows two boot voltage options of 1.0 V and 1.5 V

programmed by an external 1% resistor Rvboot from Vboot

pin to GND, which programs SVID address as well. Both

values are set on power up and cannot be changed after the

initial power up sequence is complete.

Table 7. BOOT VOLTAGE AND SVID ADDRESS CONFIGURATION

Rvboot

(W)

Vboot Pin Voltage (mV)

Address

Vboot

(V)

Min Typ Max

0 0 0 102 0x0 1.0

14.0k 102 140 180 0x1 1.0

22.1k180 219 258 0x2 1.0

30.1k258 301 344 0x3 1.0

39.2k344 391 438 0x4 1.0

48.7k438 484 531 0x5 1.0

57.6k531 578 625 0x6 1.0

68.1k625 676 727 0x7 1.0

78.7k727 781 836 0x8 1.0

88.7k836 894 953 0x0 1.5

100k953 1007 1062 0x1 1.5

113k1062 1125 1188 0x2 1.5

124k1188 1250 1312 0x3 1.5

137k1312 1378 1445 0x4 1.5

150k1445 1511 1578 0x5 1.5

165k1578 1648 1719 0x6 1.5

178k1719 1789 1859 0x7 1.5

196k1859 1950 −0x8 1.5

Switching Frequency

Switching frequency is programmed by a resistor RFREQ

to ground at the FREQ pin. The typical frequency range is

from 500 kHz to 1.2 MHz. The FREQ pin provides

approximately 2 V out and the source current is mirrored

into the internal ramp generator. The switching frequency

can be found in Figure 7 with a given RFREQ. The frequency

shown in Figure 7 is under condition of 10 A output current

at VID = 1 V. The frequency has a variation over VID

voltage and loading current, which maintains similar output

ripple voltage over different operation condition. Figure 8

shows frequency variations over the VID voltage range.

13nn 1200 1100 1nnn 900 800 Frequency (kHz) mu 600 sun Ann 300 9 11 V|D= 1,0V, ID: IDA +Vm a—w. _._Vm ,—Vm +w. 13 15 17 19 Ring“ kOhm) :sv =8V :12v =16V =zuv 21 23 25 mm: 11k0hm,lo = 10A 1000 900 800 )5 \W. 700 800 500 d5 // 2/ a2? —-— Vin:6V —— Vin:8V —— Vin:12V Frequency (kHz) 7/2; —-— Vin:16V —:— vin=zov 400 W 300 200 0.2 0.4 0.8 0.8 1 1. VID(V) 2 1.4 1.6

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Figure 7. Switching Frequency vs. RFREQ

Figure 8. Switching Frequency vs. VID Voltage

Remote Voltage Sense

A high performance differential amplifier is provided to

accurately sense the output voltage of the regulator. The

VSP and VSN inputs should be connected to the regulator’s

output voltage sense points. The output (DIFOUT) of the

remote sense amplifier is a sum of the error voltage (between

the output VSP−VSN and the DAC) and a 1.3 V DC bias.

VDIFOUT +ǒVVSP *VVSNǓ)ǒ1.3 V *VDACǓ(eq. 1)

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The DIFOUT signal then goes through a compensation

network and into the inverting input (FB pin) of an error

amplifier. The non−inverting input of the error amplifier is

connected to the same 1.3 V used for the differential sense

amplifier output bias.

Current

Sense

CSCOMP

CSREF

CSSUM

LDCR

Ccs1

Rcs2

Rcs3

VOUT

Vcs

Rcs1

Ccs2

Rcs_NTC

IOUT

0.5

VDROOP

ILIM 37

RILIM

ICCMAX

IOUT

ILIM

IOUT 36

RIOUT

ICCMAX 35

RICCMAX

Figure 9. Differential Current−Sense Circuit Diagram

Differential Current Sense

The differential current−sense circuit diagram is shown in

Figure 9. An internally−used voltage signal Vcs,

representing the inductor current level, is the voltage

difference between CSREF and CSCOMP. The output side

of the inductor is used to create a low impedance virtual

ground. The current−sense amplifier actively filters and

gains up the voltage applied across the inductor to recover

the voltage drop across the inductor’s DC resistance (DCR).

RCS_NTC is placed close to the inductor to sense the

temperature. This allows the filter time constant and gain to

be a function of the Rth_NTC resistor and compensate for

the change in the DCR with temperature. The DC gain in the

current sensing loop is

GCS +

VCS

VDCR

VCSREF *VCSCOMP

IOUT @DCR +

RCS

RCS3

(eq. 2)

Where

RCS +RCS2 )

RCS1 @RCS_NTC

RCS1 )RCS_NTC

(eq. 3)

The values of Rcs1 and Rcs2 are set based on a 220k NTC

thermistor and the temperature effect of the inductor and

thus usually they should not need to be changed. The gain

Gcs can be adjusted by the value change of the Rcs3 resistor

to provide about 100 mV in Vcs at full load.

In order to recover the inductor DCR voltage drop current

signal, the pole frequency in the CSCOMP filter should be

set equal to the zero from the output inductor, that means

CCS1 )CCS2 +L

DCR @RCS

(eq. 4)

Ccs1 and Ccs2 are in parallel to allow for a fine tuning of

the time constant using commonly available values.

Over Current Protection

The NCP81109F provides two different types of current

limit protection. Current limits are programmed with a

resistor RILIM between the CSCOMP pin and the ILIM pin.

The current from the ILIM pin to this resistor is then

compared to two internal currents (10 mA and 15 mA)

corresponding to two different current limit thresholds ILIM

and ILIM_Fast (150% of ILIM level). If the ILIM pin

current exceeds the 10 mA level, an internal latch−off timer

starts. The controller shuts down if the fault is not removed

after 50 ms. If the current into the pin exceeds 15 mA the

controller will shut down immediately. To recover from an

OCP fault the EN pin must be cycled low.

cs OVP Thresham vsPrsz DAG Rfmmw" Faun / T (VSP snarl «2 ground) Tnggered Ram own Latgged NSF sharl 1a gmund]

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The value of RILIM can be designed using the following

equation with a required over current protection threshold

ILIM and a known current−sense network.

RILIM +

VCS@ILIM

10 m+

RCS

RCS3

@ILIM_PK @DCR @105

(eq. 5)

RCS

RCS3

@ǒILIM )ǒVIN *VOUTǓ@VOUT

2@L@FSW @VIN Ǔ@DCR @105

ICC_MAX

The SVID interface conveys the platform ICC_MAX

value to the CPU by register 21h. A resistor R_ICCMAX

from the IMAX pin to ground programs this register at the

time the part is enabled. A 10 mA current is sourced from this

pin to generate a voltage on the program resistor. The value

of the register is 1A per LSB and is set by the equation below.

The resistor value should be no less than 10 k.

ICC_MAX21h +

RICCMAX @10 m@64

2+RICCMAX @3.2 @10−4

(eq. 6)

IOUT

The IOUT pin sources a current equal to the ILIM sink

current gained by the IOUT Current Gain (10 typ.). The

voltage of the IOUT pin is monitored by the internal A/D

converter and should be scaled with an external resistor to

ground such that a load equal to ICCMAX generates a 2 V

signal on IOUT. A pull−up resistor to 5 V VCC can be used

to offset the IOUT signal positive if needed.

RIOUT +2

10 @VCS@ICC_MAX @RILIM

(eq. 7)

RCS

RCS3

@ICC_MAX @DCR

@RILIM

Input UVLO Protection

NCP81109F monitors supply voltages at the VCC pin and

the VIN pins in order to provide under voltage protection. If

either supply drops below its threshold, the controller will

shut down the outputs. Upon recovery of the supplies, the

controller reenters its startup sequence, and soft start begins.

Output Under−Voltage Protection

The output voltage is monitored by a dedicated

differential amplifier. If the output falls below target by

more than “Under Voltage Threshold below DAC−Droop”,

the UVL comparator sends the VR_RDY signal low.

Output Over−Voltage Protection

During normal operation the output voltage is monitored

at the differential inputs VSP and VSN. If the output voltage

exceeds the DAC voltage by “Over Voltage Threshold above

DAC”, GH will be forced low, and GL will go high. After the

OVP trips, the DAC ramps slowly down to zero to avoid a

negative output voltage spike during shutdown. If the

DAC+OVP Threshold drops below the output, GL will

again go high, and will toggle between low and high as the

output voltage follows the DAC+OVP Threshold down.

When the DAC gets to zero, the GH will be held low and the

GL will remain high. To reset the part, the EN pin must be

cycled low. During soft−start, the OVP threshold is set to

2.9 V. This allows the controller to start up without false

triggering the OVP.

(a) Normal Operation Mode (b) During Start Up

Figure 10. Function of Over Voltage Protection

0 some and thermal alcn circuii diagram is shown is sourced out the Ihc TC Ihcrmismr R_NTC (100 k9 iyp.). iwo rosismis R_CUMP1 1: he y’D ml d in svm mgi‘ cr 1711i Usually the umnnismr is placed c In) a 11m spot like inductor or NCP81 109]: iiscli. A 1(1le Murnla 9F ____________ \ \ E] SE \\ l | I / / / - E] ,/ DR“: 3 1 \ : E] ALERYN \\ 3H— \ \ I —/

NCP81109F

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Temperature Sense and Thermal Alert

The NCP81109F provides an external temperature sense

and a thermal alert in normal operation mode. The

temperature sense and thermal alert circuit diagram is shown

in Figure 11. A precision current ITSENSE is sourced out the

output of the TSENSE pin to generate a voltage across the

temperature sense network, which consists of a NTC

thermistor R_NTC (100 kW typ.), two resistors R_COMP1

(0 W typ.) and R_COMP2 (8.2 kW typ.), and a filter

capacitor C_Filter (0.1 mF typ.). The voltage on the

temperature sense input is sampled by the internal A/D

converter and then digitally converted to temperature and

stored in SVID register 17h. Usually the thermistor is placed

close to a hot spot like inductor or NCP81109F itself. A 100k

NTC thermistor similar to the Murata

NCP15WF104D03RC should be used. The NCP81109F

also monitors the voltage at the TSENSE pin and compares

the voltage to internal thresholds and assert ALERT# or

VRHOT# once it trips the thresholds. The DC voltage at

TSENSE pin can be calculated by

VTSENSE +ITSENSE @ǒRCOMP1 )

RCOMP2 @RNTC_T

RCOMP2 )RNTC_TǓ

(eq. 8)

RNTC_T is the resistance of R_NTC at an absolute

temperature T, which is obtained by

RNTC_T +RNTC_T0@expǒB@ǒ1

T*1

T0ǓǓ

(eq. 9)

where RNTC_T0 is a known resistance of R_NTC at an

absolute temperature T0, and B is the B−constant of R_NTC.

34 TSENSE

3ALERT#

R_NTC R_COMP1

3.3V

ALERT#

Thermal

Management

R_COMP2

C_Filter

1VRHOT#

VRHOT#

Figure 11. Temperature Sense and Thermal Alert Circuit Diagram

NCP81109F

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LAYOUT GUIDELINES

Electrical Layout Considerations

Good electrical layout is a key to make sure proper

operation, high efficiency, and noise reduction. Electrical

layout guidelines are:

−Power Paths: Use wide and short traces for power

paths (such as VIN, VOUT, SW, and PGND) to reduce

parasitic inductance and high−frequency loop area. It is

also good for efficiency improvement.

−Power Supply Decoupling: The device should be well

decoupled by input capacitors and input loop area

should be as small as possible to reduce parasitic

inductance, input voltage spike, and noise emission.

Usually, a small low−ESL MLCC is placed very close

to VIN and PGND pins.

−VCC Decoupling: Place decoupling caps as close as

possible to the controller VCC and VCCP pins. The

filter resistor at VCC pin should be not higher than

2.2 W to prevent large voltage drop.

−Switching Node: SW node should be a copper pour,

but compact because it is also a noise source.

−Bootstrap: The bootstrap cap and an option resistor

need to be very close and directly connected between

pin 8 (BST) and pin 10 (SW). No need to externally

connect pin 10 to SW node because it has been

internally connected to other SW pins.

−Ground: It would be good to have separated ground

planes for PGND and GND and connect the two planes

at one point. Directly connect GND pin to the exposed

pad and then connect to GND ground plane through

vias.

−Voltage Sense: Use Kelvin sense pair and arrange a

“quiet” path for the differential output voltage sense.

−Current Sense: Careful layout for current sensing is

critical for jitter minimization, accurate current

limiting, and IOUT reporting. The filter cap from

CSCOMP to CSREF should be close to the controller.

The temperature compensating thermistor should be

placed as close as possible to the inductor. The wiring

path should be kept as short as possible and well away

from the switch node.

−Compensation Network: The small feedback cap from

COMP to FB should be as close to the controller as

possible. Keep the FB traces short to minimize their

capacitance to ground.

−SVID Bus: The Serial VID bus is a high speed data bus

and the bus routing should be done to limit noise

coupling from the switching node. The signals should

be routed with the Alert# line in between the SVID

clock and SVID data lines. The SVID lines must be

ground referenced and each line’s width and spacing

should be such that they have nominal 50 W impedance

with the board stackup.

Thermal Layout Considerations

Good thermal layout helps high power dissipation from a

small package with reduced temperature rise. Thermal

layout guidelines are:

−The exposed pads must be well soldered on the board.

−A four or more layers PCB board with solid ground

planes is preferred for better heat dissipation.

−More free vias are welcome to be around IC and

underneath the exposed pads to connect the inner

ground layers to reduce thermal impedance.

−Use large area copper pour to help thermal conduction

and radiation.

−Do not put the inductor to be too close to the IC, thus

the heat sources are distributed.

2x \ \ outsc ‘ ‘ PM? ? 2" TOP VIEW .- E A17 f f g "07: ‘ SIDE VIEW \\ D3++ DEYAILA T 5 E3 nsz c mun uuuuu 25 + E4 6 12 m} \ V ‘nnnnnﬂﬁfiljhﬁ $0t0®CAB uuuuu uuuuuu nnnn‘ nnnnn 43x b $ n.1u@ c A \ a‘ SUPPLEMENTAL n.05@ c "01:: BOTTOM VIEW BOTTOM VIEW SOLDERING FOOTPRINT“ 630 a 451 L ﬁﬁﬁuuuﬂuuuu 45x \ # 025;r ‘ E 2:19 ‘ E i ,7, 777E 630 m] ‘ E T - 5 Pimp-1% 1 E 4 IJIJDH pnnnn \ \ D‘MENS‘ONS M‘LUMETER ‘Fov addinona‘ Infovmahcn on em Fla-Free snategy and some detai‘s‘ p‘ease download the ON Semiconducmr Soldenng Mounllng Techniques Reference Manuah SOLDERRM/D, hllp://onsemi.com 27

NCP81109F

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PACKAGE DIMENSIONS

QFN48 6x6, 0.4P

CASE 485CJ

ISSUE A

SEATING

NOTE 4

0.15 C

(A3) A

48X

BOTTOM VIEW

DETAIL A

TOP VIEW

SIDE VIEW

DA B

0.15 C

PIN ONE

REFERENCE

0.10 C

0.08 C

eA0.10 B

0.05 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS

MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS

THE TERMINALS.

5. POSITIONAL TOLERANCE APPLIES TO ALL THREE EXPOSED

PADS IN BOTH X AND Y AXIS.

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 −−− 0.05

A3 0.20 REF

b0.15 0.25

D6.00 BSC

D2 4.53 4.73

E6.00 BSC

2.06E2 1.86

e0.40 BSC

L0.25 0.45

L1 −−− 0.15

NOTE 3

PLANE

DIMENSIONS: MILLIMETERS

0.25

4.81

0.40

2.09

48X

6.30

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

e/2

DETAIL B

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTION

G3 1.45 BSC

PITCH

DETAIL C

D3 1.64 1.84

D4 2.42 2.62

2.61E3 2.41

2.50E4 2.30

G4 1.06 BSC

H2 1.40 BSC

H3 1.19 BSC

L2 0.15 REF

H4 1.10 BSC

48X

0.10 BC

BOTTOM VIEW

DETAIL C

SUPPLEMENTAL

G3 G4

NOTE 5

0.58

48X

2.54

4.80

2.661.91

RECOMMENDED

D5 4.58 4.78

m J and

NCP81109F

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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

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PUBLICATION ORDERING INFORMATION

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Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

NCP81109F/D

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