MAX5590-95 Datasheet by Maxim Integrated

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lVI/JXI/VI “mum-E Buffere ’C to +85° [VI/JXIIVI
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General Description
The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-out-
put digital-to-analog converters (DACs) offer buffered
outputs and a 3µs maximum settling time at the 12-bit
level. The DACs operate from a +2.7V to +5.25V analog
supply and a separate +1.8V to +5.25V digital supply.
The 20MHz 3-wire serial interface is compatible with
SPI™, QSPI™, MICROWIRE™, and digital signal
processor (DSP) protocol applications. Multiple devices
can share a common serial interface in direct-access or
daisy-chained configuration. The MAX5590–MAX5595
provide two multifunction, user-programmable, digital
I/O ports. The externally selectable power-up states of
the DAC outputs are either zero scale, midscale, or full
scale. Software-selectable FAST and SLOW settling
modes decrease settling time in FAST mode, or reduce
supply current in SLOW mode.
The MAX5590/MAX5591 are 12-bit DACs, the MAX5592/
MAX5593 are 10-bit DACs, and the MAX5594/
MAX5595 are 8-bit DACs. The MAX5590/MAX5592/
MAX5594 provide unity-gain-configured output buffers,
while the MAX5591/MAX5593/MAX5595 provide force-
sense-configured output buffers. The MAX5590–
MAX5595 are specified over the extended -40°C to
+85°C temperature range, and are available in space-
saving 24-pin and 28-pin TSSOP packages.
Applications
Portable Instrumentation
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Automatic Tuning
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Controls
Motion Control
Microprocessor (µP)-Controlled Systems
Power Amplifier Control
Fast Parallel-DAC to Serial-DAC Upgrades
Features
oOctal, 12/10/8-Bit Serial DACs in TSSOP Packages
o3µs (max) 12-Bit Settling Time to 1/2 LSB
oIntegral Nonlinearity:
1 LSB (max) MAX5590/MAX5591 A-Grade (12-Bit)
1 LSB (max) MAX5592/MAX5593 (10-Bit)
1/2 LSB (max) MAX5594/MAX5595 (8-Bit)
oGuaranteed Monotonic, ±1 LSB (max) DNL
oTwo User-Programmable Digital I/O Ports
oSingle +2.7V to +5.25V Analog Supply
o+1.8V to AVDD Digital Supply
o20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSP-
Compatible Serial Interface
oGlitch-Free Outputs Power Up to Zero Scale,
Midscale, or Full Scale Controlled by PU Pin
oUnity-Gain or Force-Sense-Configured Output
Buffers
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-2983; Rev 3; 1/10
*
Future product—contact factory for availability. Specifications
are preliminary.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide and Pin Configurations appear at end of data
sheet.
EVALUATION KIT
AVAILABLE
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PART TEMP RANGE PIN-PACKAGE
MAX5590AEUG+* -40°C to +85°C 24 TSSOP
MAX5590BEUG+ -40°C to +85°C 24 TSSOP
MAX5591AEUI+* -40°C to +85°C 28 TSSOP
MAX5591BEUI+ -40°C to +85°C 28 TSSOP
MAX5592EUG+ -40°C to +85°C 24 TSSOP
MAX5593EUI+ -40°C to +85°C 28 TSSOP
MAX5594EUG+ -40°C to +85°C 24 TSSOP
MAX5595EUI+ -40°C to +85°C 28 TSSOP
[VI/J XI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for
AVDD = 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to DVDD........................................................................±6V
AGND to DGND ..................................................................±0.3V
AVDD to AGND, DGND.............................................-0.3V to +6V
DVDD to AGND, DGND ............................................-0.3V to +6V
FB_, OUT_,
REF to AGND........-0.3V to the lower of (AVDD + 0.3V) or +6V
SCLK, DIN, CS, PU,
DSP to DGND .......-0.3V to the lower of (DVDD + 0.3V) or +6V
UPIO1, UPIO2
to DGND ...............-0.3V to the lower of (DVDD + 0.3V) or +6V
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (TA= +70°C)
24-Pin TSSOP (derate 13.9mW/°C above +70°C) .....1111mW
28-Pin TSSOP (derate 14mW/°C above +70°C) ........1117mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY
MAX5590/MAX5591 12
MAX5592/MAX5593 10Resolution N
MAX5594/MAX5595 8
Bits
MAX5590A/MAX5591A (12-bit) ±1
MAX5590B/MAX5591B (12-bit) ±2 ±4
MAX5592/MAX5593 (10-bit) ±0.5 ±1
Integral Nonlinearity INL
VREF = 2.5V at
AVDD = 2.7V and
VREF = 4.096V at
AVDD = 5.25V
(Note 2) MAX5594/MAX5595 (8-bit) ±0.125 ±0.5
LSB
Differential Nonlinearity DNL Guaranteed monotonic (Note 2) ±1 LSB
M AX 5590A/M AX 5591A ( 12- b i t) , d eci m al cod e = 40 ±5
M AX 5590B/M AX 5591B ( 12- b i t) , d eci m al cod e = 40 ±5 ±25
MAX5592/MAX5593 (10-bit), decimal code = 10 ±5 ±25
Offset Error VOS
MAX5594/MAX5595 (8-bit), decimal code = 3 ±5 ±25
mV
Offset-Error Drift 5ppm of
FS/°C
MAX5590A/MAX5591A (12-bit) ±4
MAX5590B/MAX5590B (12-bit) ±20 ±40
MAX5592/MAX5593 (10-bit) ±5 ±10
Gain Error GE Full-scale output
MAX5594/MAX5595 (8-bit) ±2 ±3
LSB
Gain-Error Drift 1ppm of
FS/°C
lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for
AVDD = 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-Supply Rejection
Ratio PSRR Full-scale output, AVDD = 2.7V to 5.25V 200 µV/V
REFERENCE INPUT
Reference Input Range VREF 0.25 AVDD V
Reference Input
Resistance RREF Normal operation (no code dependence) 145 200 kΩ
Reference Leakage
Current Shutdown mode 0.5 1 µA
DAC OUTPUT CHARACTERISTICS
Unity gain 85
SLOW mode, full scale Force sense 67
Unity gain 140
Output Voltage Noise
FAST mode, full scale Force sense 110
µVRMS
Unity-gain output 0 AVDD
Output Voltage Range
(Note 3) Force-sense output 0 AVDD / 2 V
DC Output Impedance 38 Ω
AVDD = 5V, OUT_ to AGND, full scale, FAST mode 57
Short-Circuit Current AVDD = 3V, OUT_ to AGND, full scale, FAST mode 45 mA
Power-Up Time From VDD applied until interface is functional 30 60 µs
Wake-Up Time Coming out of shutdown, outputs settled 40 µs
Output OUT_ and FB_
Open-Circuit Leakage
Current
Programmed in shutdown mode, force-sense
outputs only 0.01 µA
DIGITAL OUTPUTS (UPIO_)
Output High Voltage VOH ISOURCE = 2mA DVDD -
0.5 V
Output Low Voltage VOL ISINK = 2mA 0.4 V
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)
DVDD ≥ 2.7V 2.4
Input High Voltage VIH DVDD < 2.7V 0.7 x
DVDD
V
DVDD > 3.6V 0.8
2.7V ≤ DVDD ≤ 3.6V 0.6
Input Low Voltage VIL
DVDD < 2.7V 0.2
V
Input Leakage Current IIN ±0.1 ±1 µA
Input Capacitance CIN 10 pF
[VIIJXIIVI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for
AVDD = 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PU INPUT
Input High Voltage VIH-PU DVDD -
200mV V
Input Low Voltage VIL-PU 200 mV
Input Leakage Current IIN-PU PU still considered unconnected when connected to
a tri-state bus ±200 nA
DYNAMIC PERFORMANCE
FAST mode 3.6
Voltage-Output Slew
Rate SR SLOW mode 1.6 V/µs
M AX 5590/M AX 5591 fr om cod e 322 to
cod e 4095 to 1/2 LS B23
M AX 5592/M AX 5593 fr om cod e 10 to
cod e 1023 to 1/2 LS B1.5 3
FAST
mode
MAX5594/MAX5595 fr om cod e 3 to
code 255 to 1/2 LSB 12
M AX 5590/M AX 5591 fr om cod e 322 to
cod e 4095 to 1/2 LS B36
MAX5592/MAX5593 fr om cod e 10 to
code 1023 1/2 LSB 2.5 6
Voltage-Output Settling
Time (Note 5)
SLOW
mode
MAX5594/MAX5595 fr om cod e 3 to
code 255 to 1/2 LSB 24
µs
FB_ Input Voltage 0V
REF / 2 V
FB_ Input Current 0.1 µA
Unity gain 200
Reference -3dB
Bandwidth (Note 6) Force sense 150 kHz
Digital Feedthrough CS = DVDD, code = zero scale, any digital input
from 0 to DVDD and DVDD to 0, f = 100kHz 0.1 nV-s
Digital-to-Analog Glitch
Impulse Major carry transition 2 nV-s
DAC-to-DAC Crosstalk (Note 4) 15 nV-s
\DvDDrSHDN) lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for
AVDD = 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
Range AVDD
2.70 5.25
V
Digital Supply Voltage
Range DVDD 1.8
AVDD
V
Unity gain 1.5 3.2
SLOW mode, all digital inputs
at DGND or DVDD, no load,
VREF = 4.096V Force sense 2.4 4.8
Unity gain 2.5 8
Operating Supply
Current
IAVDD
+
IDVDD FAST mode, all digital inputs
at DGND or DVDD, no load,
VREF = 4.096V Force sense 3.4 8
mA
Shutdown Supply
Current
IAV D D ( S H D N )
+
ID V D D
(
S H D N
)
No clocks, all digital inputs at DGND or DVDD, all
DACs in shutdown mode 0.5 1 µA
Note 1: For the force-sense versions, FB_ is connected to its respective OUT_. VOUT (max) = VREF / 2, unless otherwise noted.
Note 2: Linearity guaranteed from decimal code 40 to code 4095 for the MAX5590B/MAX5591B (12-bit, B-grade), code 10 to code
1023 for the MAX5592/MAX5593 (10-bit), and code 3 to code 255 for the MAX5594/MAX5595 (8-bit).
Note 3: Represents the functional range. The linearity is guaranteed at VREF = 2.5V (for AVDD from 2.7V to 5.25V), and VREF =
4.096V (for AVDD = 4.5V to 5.25V). See the
Typical Operating Characteristics
section for linearity at other voltages.
Note 4: DC crosstalk is measured as follows: outputs of DACA–DACH are set to full scale and the output of DACH is measured.
While keeping DACH unchanged, the outputs of DACA–DACG are transitioned to zero scale and the ∆VOUT of DACH is
measured.
Note 5: Guaranteed by design.
Note 6: The reference -3dB bandwidth is measured with a 0.1VP-P sine wave on VREF and with full-scale input code.
[VIIJXIIVI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1)
(DVDD = 2.7V to 5.25V, VAGND = 0V, VDGND = 0V, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency fSCLK 2.7V < DVDD < 5.25V 20 MHz
SCLK Pulse-Width High tCH (Note 7) 20 ns
SCLK Pulse-Width Low tCL (Note 7) 20 ns
CS Fall to SCLK Rise Setup Time tCSS 10 ns
SCLK Rise to CS Rise Hold Time tCSH 5ns
SCLK Rise to CS Fall Setup tCS0 10 ns
DIN to SCLK Rise Setup Time tDS 12 ns
DIN to SCLK Rise Hold Time tDH 5ns
SCLK Rise to DOUTDC1 Valid
Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 mode 30 ns
SCLK Fall to DOUT_ Valid
Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode 30 ns
CS Rise to SCLK Rise Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 10 ns
CS Pulse-Width High tCSW 45 ns
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when Exiting
DOUTDC0, DOUTDC1, and UPIO
Modes
tDOZ CL = 20pF, from end of write cycle to UPIO_
in high impedance 100 ns
DOUTRB Tri-State Time from CS
Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_
in high impedance 20 ns
DOUTRB Tri-State Enable Time
from 8th SCLK Rise tZEN CL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state 0ns
LDAC Pulse-Width Low tLDL Figure 5 20 ns
LDAC Effective Delay tLDS Figure 6 100 ns
CLR, MID, SET Pulse-Width Low tCMS Figure 5 20 ns
GPO Output Settling Time tGP Figure 6 100 ns
GPO Output High-Impedance
Time tGPZ 100 ns
lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 7
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DVDD = 1.8V to 5.25V, VAGND = 0V, VDGND = 0V, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency fSCLK 1.8V < DVDD < 5.25V 10 MHz
SCLK Pulse-Width High tCH (Note 7) 40 ns
SCLK Pulse-Width Low tCL (Note 7) 40 ns
CS Fall to SCLK Rise Setup Time tCSS 20 ns
SCLK Rise to CS Rise Hold Time tCSH 0ns
SCLK Rise to CS Fall Setup tCS0 10 ns
DIN to SCLK Rise Setup Time tDS 20 ns
DIN to SCLK Rise Hold Time tDH 5ns
SCLK Rise to DOUTDC1 Valid
Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 mode 60 ns
SCLK Fall to DOUT_ Valid
Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode 60 ns
CS Rise to SCLK Rise Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 20 ns
CS Pulse-Width High tCSW 90 ns
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
tDOZ CL = 20pF, from end of write cycle to UPIO_
in high impedance 200 ns
DOUTRB Tri-State Time from CS
Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_
in high impedance 40 ns
DOUTRB Tri-State Enable Time
from 8th SCLK Rise tZEN CL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state 0ns
LDAC Pulse-Width Low tLDL Figure 5 40 ns
LDAC Effective Delay tLDS Figure 6 200 ns
CLR, MID, SET Pulse-Width Low tCMS Figure 5 40 ns
GPO Output Settling Time tGP Figure 6 200 ns
GPO Output High-Impedance
Time tGPZ 200 ns
[VIIJXIIVI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
8 _______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2)
(DVDD = 2.7V to 5.25V, VAGND = 0V, VDGND = 0V, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency fSCLK 2.7V < DVDD < 5.25V 20 MHz
SCLK Pulse-Width High tCH (Note 7) 20 ns
SCLK Pulse-Width Low tCL (Note 7) 20 ns
CS Fall to SCLK Fall Setup Time tCSS 10 ns
DSP Fall to SCLK Fall Setup Time tDSS 10 ns
SCLK Fall to CS Rise Hold Time tCSH 5ns
SCLK Fall to CS Fall Delay tCS0 10 ns
SCLK Fall to DSP Fall Delay tDS0 10 ns
DIN to SCLK Fall Setup Time tDS 12 ns
DIN to SCLK Fall Hold Time tDH 5ns
SCLK Rise to DOUT_ Valid
Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode 30 ns
SCLK Fall to DOUT_ Valid
Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 mode 30 ns
CS Rise to SCLK Fall Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 10 ns
CS Pulse-Width High tCSW 45 ns
DSP Pulse-Width High tDSW 20 ns
DSP Pulse-Width Low tDSPWL (Note 8) 20 ns
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
tDOZ CL = 20pF, from end of write cycle to UPIO_
in high impedance 100 ns
DOUTRB Tri-State Time from CS
Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_
in high impedance 20 ns
DOUTRB Tri-State Enable Time
from 8th SCLK Fall tZEN CL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state 0ns
LDAC Pulse-Width Low tLDL Figure 5 20 ns
LDAC Effective Delay tLDS Figure 6 100 ns
CLR, MID, SET Pulse-Width Low tCMS Figure 5 20 ns
GPO Output Settling Time tGP Figure 6 100 ns
GPO Output High-Impedance
Time tGPZ 100 ns
lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 9
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)
(DVDD = 1.8V to 5.25V, VAGND = 0V, VDGND = 0V, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency fSCLK 1.8V < DVDD < 5.25V 10 MHz
SCLK Pulse-Width High tCH (Note 7) 40 ns
SCLK Pulse-Width Low tCL (Note 7) 40 ns
CS Fall to SCLK Fall Setup Time tCSS 20 ns
DSP Fall to SCLK Fall Setup Time tDSS 20 ns
SCLK Fall to CS Rise Hold Time tCSH 0ns
SCLK Fall to CS Fall Delay tCS0 10 ns
SCLK Fall to DSP Fall Delay tDS0 15 ns
DIN to SCLK Fall Setup Time tDS 20 ns
DIN to SCLK Fall Hold Time tDH 5ns
SCLK Rise to DOUT_ Valid
Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode 60 ns
SCLK Fall to DOUT_ Valid
Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 mode 60 ns
CS Rise to SCLK Fall Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 20 ns
CS Pulse-Width High tCSW 90 ns
DSP Pulse-Width High tDSW 40 ns
DSP Pulse-Width Low tDSPWL (Note 8) 40 ns
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
tDOZ CL = 20pF, from end of write cycle to UPIO_
in high impedance 200 ns
DOUTRB Tri-State Time from CS
Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_
in high impedance 40 ns
DOUTRB Tri-State Enable Time
from 8th SCLK Fall tZEN CL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state 0ns
LDAC Pulse-Width Low tLDL Figure 5 40 ns
LDAC Effective Delay tLDS Figure 6 200 ns
CLR, MID, SET Pulse-Width Low tCMS Figure 5 40 ns
GPO Output Settling Time tGP Figure 6 200 ns
GPO Output High-Impedance
Time tGPZ 200 ns
Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low
and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of
operation.
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
10 ______________________________________________________________________________________
-4
-2
-3
-1
0
1
2
3
4
0 1024 2048 3072 4095
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
MAX5590-95 toc01
DIGITAL INPUT CODE
INL (LSB)
B-GRADE
-1.00
-0.50
-0.75
-0.25
0
0.25
0.50
0.75
1.00
0 256 512 768 1023
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
MAX5590-95 toc02
DIGITAL INPUT CODE
INL (LSB)
-0.50
-0.25
0
0.25
0.50
0 64 128 192 255
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
MAX5590-95 toc03
DIGITAL INPUT CODE
INL (LSB)
-0.50
-0.25
0
0.25
0.50
0 1024 2048 3072 4095
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
MAX5590-95 toc04
DIGITAL INPUT CODE
DNL (LSB)
B-GRADE
-0.2
-0.1
0
0.1
0.2
0 256 512 768 1023
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
MAX5590-95 toc05
DIGITAL INPUT CODE
DNL (LSB)
-0.050
-0.025
0
0.025
0.050
0 64 128 192 255
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
MAX5590-95 toc06
DIGITAL INPUT CODE
DNL (LSB)
-4
-2
-3
0
-1
1
2
3
4
1.0 2.0 2.51.5 3.0 3.5 4.0 4.5 5.0
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE (12-BIT)
MAX5590-95 toc07
VREF (V)
INL (LSB)
B-GRADE
MIDSCALE -0.5
-0.3
-0.4
-0.1
-0.2
0.1
0
0.2
0.4
0.3
0.5
1.0 20 2.51.5 3.0 3.5 4.0 4.5 5.0
DIFFERENTIAL NONLINEARITY
vs. REFERENCE VOLTAGE (12-BIT)
MAX5590-95 toc08
VREF (V)
DNL (LSB)
B-GRADE
MIDSCALE
-4
0
-2
-3
-1
2
4
3
1
-40 10-15 35 60 85
INTEGRAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
MAX5590-95 toc09
TEMPERATURE (°C)
INL (LSB)
B-GRADE
MIDSCALE
Typical Operating Characteristics
(AVDD = DVDD = 5V, VREF = 4.096V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = unconnected, TA= +25°C, unless otherwise
noted.)
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________
11
-0.2
0
-0.1
0.1
0.2
-40 10-15 35 60 85
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
MAX5590-95 toc10
TEMPERATURE (°C)
DNL (LSB)
B-GRADE
MIDSCALE
0
1
2
3
4
5
0 1024 2048 3072 4095
SUPPLY CURRENT
vs. DIGITAL INPUT CODE (FORCE-SENSE)
MAX5590-95 toc11
DIGITAL INPUT CODE
SUPPLY CURRENT (mA)
12-BIT
NO LOAD
0
1
2
3
0 1024 2048 3072 4095
SUPPLY CURRENT
vs. DIGITAL INPUT CODE (UNITY GAIN)
MAX5590-95 toc12
DIGITAL INPUT CODE
SUPPLY CURRENT (mA)
12-BIT
NO LOAD
0
1
2
3
4
2.70 3.40 4.10 4.80 5.25
SUPPLY CURRENT
vs. SUPPLY VOLTAGE (FORCE-SENSE)
MAX5590-95 toc13
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SLOW MODE
FAST MODE
AVDD = DVDD
NO LOAD
0
0.5
1.0
1.5
2.0
2.5
3.0
2.70 3.40 4.10 4.80 5.25
SUPPLY CURRENT
vs. SUPPLY VOLTAGE (UNITY GAIN)
MAX5590-95 toc14
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
AVDD = DVDD
NO LOAD
SLOW MODE
FAST MODE
0
20
10
30
50
40
60
2.70 4.103.40 4.80 5.25
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5590-95 toc15
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (nA)
NO LOAD
FORCE SENSE
UNITY GAIN
0
1
2
4
5
3
6
7
-40 10-15 35 60 85
OFFSET ERROR vs. TEMPERATURE
MAX5590-95 toc16
TEMPERATURE (°C)
OFFSET ERROR (LSB)
CODE = 40
UNITY GAIN: 1 LSB = 1mV
FORCE SENSE: 1 LSB = 0.5mV
UNITY GAIN
FORCE SENSE
-10
-8
-4
-6
-2
0
-40 10-15 35 60 85
GAIN ERROR vs. TEMPERATURE
MAX5590-95 toc17
TEMPERATURE (°C)
GAIN ERROR (LSB)
FORCE SENSE
UNITY GAIN
UNITY GAIN: 1 LSB = 1mV
FORCE SENSE: 1 LSB = 0.5mV 0
0.5
1.5
1.0
2.0
2.5
-15 -5-10 0 5 10 15
OUTPUT VOLTAGE
vs. OUTPUT SOURCE/SINK CURRENT
MAX5590-95 toc18
IOUT (mA)
OUTPUT VOLTAGE (V)
UNITY GAIN
VREF = 4.096V
MIDSCALE
Typical Operating Characteristics (continued)
(AVDD = DVDD = 5V, VREF = 4.096V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = unconnected, TA= +25°C, unless otherwise
noted.)
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
12 ______________________________________________________________________________________
MAJOR-CARRY TRANSITION GLITCH
MAX5590-95 toc19
250ns/div
OUT_
2mV/div
CS
5V/div
SETTLING TIME POSITIVE
MAX5590-95 toc20
400ns/div
OUT_
2V/div
CS
5V/div
FULL-SCALE
TRANSITION
SETTLING TIME NEGATIVE
MAX5590-95 toc21
400ns/div
OUT_
2V/div
CS
5V/div
FULL-SCALE
TRANSITION
5
-25
1 100 100010 10,000
REFERENCE INPUT BANDWIDTH
MAX5590-95 toc22
FREQUENCY (kHz)
GAIN (dB)
-20
-15
-10
-5
0
VREF = 0.1VP-P AT 4.096VDC
UNITY GAIN
REFERENCE FEEDTHROUGH AT 1kHz
MAX5590-95 toc23
FREQUENCY (kHz)
SIGNAL AMPLITUDE (dB)
5.04.53.5 4.01.5 2.0 2.5 3.01.0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-22
-142
0.5 5.5 200µs/div
DAC-TO-DAC CROSSTALK
OUTH
1mV/div
OUTA–OUTG
2V/div
MAX5590-95 toc24
Typical Operating Characteristics (continued)
(AVDD = DVDD = 5V, VREF = 4.096V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = unconnected, TA= +25°C, unless otherwise
noted.)
1µs/div
DIGITAL FEEDTHROUGH
OUT_
(AC-COUPLED)
2mV/div
SCLK
2V/div
MAX5590-95 toc25
400µs/div
POWER-UP GLITCH
OUT_
2V/div
AVDD
2V/div
MAX5590-95 toc26
PU = DVDD
lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 13
Pin Description
PIN
MAX5590
MAX5592
MAX5594
MAX5591
MAX5593
MAX5595
NAME FUNCTION
11AV
DD Analog Supply
2 2 AGND Analog Ground
3 3 OUTA DACA Output
4, 8, 17, 21 — N.C. No Connection. Not internally connected.
5 6 OUTB DACB Output
6 7 OUTC DACC Output
7 10 OUTD DACD Output
911CS Active-Low Chip-Select Input
10 12 SCLK Serial Clock Input
11 13 DIN Serial Data Input
12 14 DSP
Clock Enable. Connect DSP to DVDD at power-up to transfer data on the rising edge
of SCLK. Connect DSP to GND to transfer data on the falling edge of SCLK.
Connect DSP to DGND at power-up to transfer data on the falling edge of SCLK.
13 15 DVDD Digital Supply
14 16 DGND Digital Ground
15 17 UPIO1 User-Programmable Input/Output 1
16 18 UPIO2 User-Programmable Input/Output 2
18 19 OUTE DACE Output
19 22 OUTF DACF Output
20 23 OUTG DACG Output
22 26 OUTH DACH Output
23 27 PU
Power-Up State Select Input. Connect PU to DVDD to set OUTA–OUTH to full scale
upon power-up. Connect PU to DGND to set OUTA–OUTH to zero upon power-up.
Leave PU unconnected at power-up to set OUTA–OUTH to midscale.
24 28 REF Reference Input
— 4 FBA Feedback for DACA
— 5 FBB Feedback for DACB
— 8 FBC Feedback for DACC
— 9 FBD Feedback for DACD
— 20 FBE Feedback for DACE
— 21 FBF Feedback for DACF
— 24 FBG Feedback for DACG
— 25 FBH Feedback for DACH
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
14 ______________________________________________________________________________________
Functional Diagrams
MAX5590
MAX5592
MAX5594
DOUT
REGISTER
16-BIT SHIFT
REGISTER
CS
SCLK
DIN
DSP
SERIAL
INTERFACE
CONTROL
MUX
AVDD
UPIO1
UPIO2
REF
PU
UPIO1 AND
UPIO2
LOGIC POWER-DOWN
LOGIC AND
REGISTER
DECODE
CONTROL
INPUT
REGISTER
A
DAC
REGISTER
A
DACA
OUTA
INPUT
REGISTER
H
DACH
OUTH
DAC
REGISTER
H
DVDD AGND DGND
lVI/lXI/l/I lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 15
Functional Diagrams (continued)
MAX5591
MAX5593
MAX5595
DOUT
REGISTER
16-BIT SHIFT
REGISTER
CS
SCLK
DIN
DSP
SERIAL
INTERFACE
CONTROL
MUX
AVDD
UPIO1
UPIO2
REF
PU
UPIO1 AND
UPIO2
LOGIC POWER-DOWN
LOGIC AND
REGISTER
DECODE
CONTROL
INPUT
REGISTER
A
DAC
REGISTER
A
DACA
OUTA
FBA
FBH
INPUT
REGISTER
H
DACH
OUTH
DAC
REGISTER
H
DVDD AGND DGND
[VI/JXIIIII
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
16 ______________________________________________________________________________________
Detailed Description
The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-out-
put DACs offer buffered outputs and a 3µs maximum
settling time at the 12-bit level. The DACs operate from a
single 2.7V to 5.25V analog supply and a separate 1.8V
to AVDD digital supply. The MAX5590–MAX5595 include
an input register and DAC register for each channel and
a 16-bit data-in/data-out shift register. The 3-wire serial
interface is compatible with SPI, QSPI, MICROWIRE, and
DSP applications. The MAX5590– MAX5595 provide two
user-programmable digital I/O ports, which are pro-
grammed through the serial interface. The externally
selectable power-up states of the DAC outputs are either
zero scale, midscale, or full scale.
Reference Input
The reference input, REF, accepts both AC and DC val-
ues with a voltage range extending from analog ground
(AGND) to AVDD. The voltage at REF sets the full-scale
output of the DACs. Determine the output voltage using
the following equations:
Unity-gain versions:
VOUT_ = (VREF x CODE) / 2N
Force-sense versions (FB_ connected to OUT_):
VOUT = 0.5 x (VREF x CODE) / 2N
where CODE is the numeric value of the DAC’s binary
input code and N is the bits of resolution. For the
MAX5590/MAX5591, N = 12 and CODE ranges from 0
to 4095. For the MAX5592/MAX5593, N = 10 and
CODE ranges from 0 to 1023. For the MAX5594/
MAX5595, N = 8 and CODE ranges from 0 to 255.
Output Buffers
The DACA and DACH output-buffer amplifiers of the
MAX5590–MAX5595 are unity-gain stable with rail-to-
rail output voltage swings and a typical slew rate
of 3.6V/µs (FAST mode). The MAX5590/MAX5592/
MAX5594 provide unity-gain outputs, while the
MAX5591/MAX5593/MAX5595 provide force-sense out-
puts. For the MAX5591/MAX5593/MAX5595, access to
the output amplifier’s inverting input provides flexibility
in output gain setting and signal conditioning (see the
Applications Information
section).
The MAX5590–MAX5595 offer FAST and SLOW settling-
time modes. In the SLOW mode, the settling time is 6µs
(max), and the supply current is 3.2mA (max). In the
FAST mode, the settling time is 3µs (max), and the sup-
ply current is 8mA (max). See the
Digital Interface
section
for settling-time mode programming details.
Use the serial interface to set the shutdown output
impedance of the amplifiers to 1kΩor 100kΩfor the
MAX5590/MAX5592/MAX5594 and 1kΩor high imped-
ance for the MAX5591/MAX5593/MAX5595. The DAC
outputs can drive a 10kΩ(typ) load and are stable with
up to 500pF (typ) of capacitive load.
Power-On Reset
At power-up, all DAC outputs power up to full scale,
midscale, or zero scale, depending on the configuration
of the PU input. Connect PU to DVDD to set OUT_ to full
scale upon power-up. Connect PU to digital ground
(DGND) at power-up to set OUT_ to zero scale. Leave
PU unconnected to set OUT_ to midscale.
Digital Interface
The MAX5590–MAX5595 use a 3-wire serial interface
that is compatible with SPI, QSPI, MICROWIRE, and DSP
protocol applications (Figures 1 and 2). Connect DSP to
DVDD before power-up to clock data in on the rising
edge of SCLK. Connect DSP to DGND before power-up
to clock data in on the falling edge of SCLK. After power-
up, the device enters DSP frame-sync mode on the first
rising edge of DSP. Refer to the
MAX5590–MAX5595
Programmer’s Handbook
for details.
The MAX5590–MAX5595 include a 16-bit input shift
register. The data is loaded into the input shift register
through the serial interface. The 16 bits can be sent in
two serial 8-bit packets or one 16-bit word (CS must
remain low until all 16 bits are transferred). The data is
loaded MSB first. For the MAX5590/MAX5591, the 16
bits consist of 4 control bits (C3–C0) and 12 data bits
(D11–D0) (see Table 1). For the 10-bit MAX5592/
MAX5593 devices, D11–D2 are the data bits and D1
and D0 are sub-bits. For the 8-bit MAX5594/
MAX5595 devices, D11–D4 are the data bits and
D3–D0 are sub-bits. Set all sub-bits to zero for optimum
performance.
Each DAC channel includes two registers: an input reg-
ister and the DAC register. At power-up, the DAC out-
put is set according to the state of PU. The DACs are
double-buffered, which allows any of the following for
each channel:
• Loading the input register without updating the DAC
register
• Updating the DAC register from the input register
• Updating the input and DAC registers simultaneously
lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 17
Table 1. Serial Write Data Format
MSB 16 BITS OF SERIAL DATA
LSB
CONTROL BITS DATA BITS
C3
C2 C1 C0 D11 D10
D9 D8 D7 D6
D5
D4 D3 D2 D1 D0
Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)
Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled)
SCLK
DIN
CS
DOUTDC1*
DOUTDC0
OR
DOUTRB*
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.
tCH
tDS
tCS0 tDH tCSH
tDO1
tDO2
tCL
tCSW tCS1
DOUT VALID
DOUT VALID
tCSS
C1 D0C2C3
SCLK
DIN
CS
DSP
DOUTDC0*
DOUTDC1
OR
DOUTRB*
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.
tCL
tDS
tCCS
tDSW tDSPWL
tD02
tD01
tDH
tCS0
tCH
C3 C2 C1 D0
tCSH
tCSW tDSS tCS1
tDS0
DOUT VALID
DOUT VALID
[MAXI/III [MAXI/VI [MAXI/III [VIIJXIIVI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
18 ______________________________________________________________________________________
SCLK
DIN
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DIN
SCLK
DVDD
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N ✕ 16
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N ✕ 16
MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
DIN
SCLK
CS
CS
MAX5590–
MAX5595
VDD
VDD
MICROWIRE
SK
SO
I/O
SCLK
DIN
DVDD
MAX5590–
MAX5595
VDD
VDD
SPI OR QSPI
SCK
MOSI
SS OR I/O CS
DSPDSP
CS
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
DIN
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DIN
SCLK
DGND
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N ✕ 16
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N ✕ 16
DSP OR SPI (CPOL = 0, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
DIN
SCLK
CS
CS
MAX5590–
MAX5595
VSS
DSP
TCLK, SCLK, OR CLKX
DT OR DX
TFS OR FSX
SCLK
DIN
DGND
MAX5590–
MAX5595
VSS
SPI OR QSPI
SCK
MOSI
SS OR I/O CS
DSPDSP
CS
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
Figure 3. MICROWIRE and SPI Single DAC Writes (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1)
Figure 4. DSP and SPI Single DAC Writes (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0)
Serial-Interface Programming Commands
Tables 2a, 2b, and 2c provide all of the serial-interface
programming commands for the MAX5590–MAX5595.
Table 2a shows the basic DAC programming com-
mands, Table 2b gives the advanced-feature program-
ming commands, and Table 2c provides the 24-bit
read commands. Figures 3 and 4 provide the serial-
interface diagrams for read and write operations.
Loading Input and DAC Registers
The MAX5590–MAX5595 contain a 16-bit shift register
that is followed by a 12-bit input register and a 12-bit
DAC register for each channel (see the
Functional
Diagrams
). Tables 3, 4, and 5 highlight a few of the
commands that handle the loading of the input and
DAC registers. See Table 2a for all DAC programming
commands.
lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 19
CONTROL BITS DATA BITS
D A T A C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
INPUT REGISTERS (A–H)
DIN 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D 3/0 D 2/0 D 1/0 D 0/0
Load input register A from shift register; DAC
registers are unchanged. DAC outputs are
unchanged.*
DIN 0 0 0 1 D11 D10 D9 D8 D7 D6 D5 D4 D 3/0 D 2/0 D 1/0 D 0/0
Load input register B from shift register; DAC
registers are unchanged. DAC outputs are
unchanged.*
DIN 0 0 1 0 D11 D10 D9 D8 D7 D6 D5 D4 D 3/0 D 2/0 D 1/0 D 0/0
Load input register C from shift register; DAC
registers are unchanged. DAC outputs are
unchanged.*
DIN 0 0 1 1 D11 D10 D9 D8 D7 D6 D5 D4 D 3/0 D 2/0 D 1/0 D 0/0
Load input register D from shift register; DAC
registers are unchanged. DAC outputs are
unchanged.*
DIN 0 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D 3/0 D 2/0 D 1/0 D 0/0
Load input register E from shift register; DAC
registers are unchanged. DAC outputs are
unchanged.*
DIN 0 1 0 1 D11 D10 D9 D8 D7 D6 D5 D4 D 3/0 D 2/0 D 1/0 D 0/0
Load input register F from shift register; DAC
registers are unchanged. DAC outputs are
unchanged.*
DIN 0 1 1 0 D11 D10 D9 D8 D7 D6 D5 D4 D 3/0 D 2/0 D 1/0 D 0/0
Load input register G from shift register; DAC
registers are unchanged. DAC outputs are
unchanged.*
DIN 0 1 1 1 D11 D10 D9 D8 D7 D6 D5 D4 D 3/0 D 2/0 D 1/0 D 0/0
Load input register H from shift register; DAC
registers are unchanged. DAC outputs are
unchanged.*
Table 2a. DAC Programming Commands
*
For the MAX5592/MAX5593 (10-bit version), D11–D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5594/MAX5595 (8-bit version),
D11–D4 are the significant bits and D3–D0 are sub-bits. Set all sub-bits to zero during the write commands.
20 [VIIJXIIVI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
20 ______________________________________________________________________________________
CONTROL BITS DATA BITS
DATA C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
SELECT BITS
DIN 1000XXXXMHMGMFMEMDMCMBMA
Load D AC r eg i ster “_”
fr om i np ut r eg i ster “_”
w hen M _ = 1. D AC r eg i ster
“_” i s unchang ed i f M _ = 0.
LOADING INPUT AND DAC REGISTERS (A–H)
DIN 1001D11D10D9D8D7D6D5D4D3/0 D2/0 D1/0 D0/0
Load all input registers
A–H from shift register;
DAC registers are
unchanged. DAC outputs
are unchanged.*
DIN 1010D11D10D9D8D7D6D5D4D3/0 D2/0 D1/0 D0/0
Load all input and DAC
registers A–H from shift
register. DAC outputs
updated.
SHUTDOWN BITS
DIN 10110000PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0
Write DACA–DACD
shutdown-mode bits.
See Table 8.
DIN 10110001XXXXXXXX
DOUTRB XXXXXXXXPDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0
Read-back DACA–DACD
shutdown-mode bits.
DIN 10110010PDH1 PDH0 PDG1 PDG0 PDF1 PDF0 PDE1 PDE0
Write DACE–DACH
shutdown-mode bits.
See Table 8.
DIN 10110011XXXXXXXX
DOUTRB XXXXXXXXPDH1 PDH0 PDG1 PDG0 PDF1 PDF0 PDE1 PDE0
Read-back DACE–DACH
shutdown-mode bits.
DIN 10110100PDCHPDCG PDCF PDCE PDCD PDCC PDCB PDCA Write DAC shutdown-
control bits.
DIN 10110101XXXXXXXX
DOUTRB XXXXXXXXPDCHPDCG PDCF PDCE PDCD PDCC PDCB PDCA
Read-back DAC
shutdown-control settings.
Table 2b. Advanced-Feature Programming Commands
X = Don’t care.
*
For the MAX5592/MAX5593 (10-bit version), D11–D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5594/MAX5595 (8-bit version),
D11–D4 are the significant bits and D3–D0 are sub-bits. Set all sub-bits to zero during the write commands.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DAGs :hXMMQOIEs—Xmmbm 25 42% 6% x x x x x x x x x x x x x x 52505 ESQ/«Eugene ummm x x x x x x x x V o o o o o 7 V 25 5 2%me m g ,9_C8<:n540n_om_§ 42%="" 6%="" x="" x="" x="" x="" x="" x="" o="" o="" o="" o="" o="" o="" 7="" v="" 25="" mtm="" .6528="" «:3="" 52¢="" .63="" 88%="" 1054995="" memmmgagmwoasa="" e:="" e="" he="" ne="" ne="" ne:="" x="" x="" x="" x="" x="" x="" x="" x="" x="" x="" 52505="" is:="" am="" a="" ma="" es="" 9:8="" m,="" 85...="" 5="" be...="" 8%,="" 28="" e9358="" oe...="" 9mm:="" x="" x="" x="" x="" x="" x="" x="" x="" x="" r="" o="" r="" r="" r="" o="" r="" 25="" e52.="" mmoumaujemzmq="" eu="" 2="" ‘05:="" .25="" we;="" 5%="" 55%="" 05%="" 55%="" 55%="" 5%="" 05%="" 15%="" x="" x="" x="" x="" x="" x="" x="" x="" 52505="" 5255358282="" x="" x="" x="" x="" x="" x="" x="" x="" r="" o="" o="" r="" r="" r="" o="" r="" 25="" :33="" ge“="" 2="" is="" 2303=""><><5 45%="" 59m="" 55%="" 55%="" new="" 5%="" 05%="" 15%="" o="" o="" o="" r="" r="" r="" o="" r="" 25="" 5.25méfm="" $.23="" mtm="" mno:.m:_._..az_._._.._.mm="" 5.22%="" 8293928="" sm:="" in:="" em:="" sm:="" ne:="" ne:="" ne:="" ne:="" x="" x="" x="" x="" x="" x="" x="" x="" 52505="" 02308282="" x="" x="" x="" x="" x="" x="" x="" x="" 2="" 2="" 2="" a="" 2="" 2="" a="" 2="" 25="" cm="" mm="" m="" 2="" «nu="" 9="" es="" mm="" b="" x="" x="" e...="" e...="" na...="" e...="" emanflmns="" o="" 7="" v="" o="" 7="" v="" o="" 7="" 25="" 8,8598u="" oe:="" m3;="" mtm=""><><>
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 21
CONTROL BITS DATA BITS
DATA C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
UPIO CONFIGURATION BITS
DIN 10110110U P S L2 U P S L1 U P 3U P 2U P 1U P 0X X
Wr i te U P IO confi g ur ati on
b i ts. S ee Tab l es 19 and 22.
DIN 1 0 1 1 0 1 1 1 X X X X X X X X
DOUTRB X X X X X X X X U P 3- 2U P 2- 2U P 1- 2U P 0- 2U P 3- 1U P 2- 1U P 1- 1U P 0- 1
Read - b ack U P IO
confi g ur ati on b i ts functi on.
SETTLING-TIME-MODE BITS
DIN 10111000S P D H S P D GS P D FS P D E S P D D S P D C S P D BS P D A
Wr i te settl i ng - ti m e b i ts for
D AC A–D AC H ( 0 = S LOW
[ d efaul t, 6µs] , 1 = FAS T
[ 3µs] ) .
DIN 1 0 1 1 1 0 0 1 X X X X X X X X
DOUTRB X X X X X X X X S P D H S P D GS P D FS P D E S P D D S P D C S P D BS P D A
Read - b ack D AC settl i ng -
ti m e b i ts.
UPIO_ AS GPI (GENERAL-PURPOSE INPUT)
DIN 1011101XXXXXXXXX
DOUTRB X X X XXXXXXXRTP2 LF2 LR2 RTP1 LF1 LR1
Read U P IO _ i np uts ( val i d
onl y w hen U P IO1 or U P IO2
i s confi g ur ed as a g ener al -
p ur p ose i np ut.) S ee the
GP I, GP OL, GP OH secti on.
CPOL AND CPHA CONTROL BITS
DIN 1 1 0 0 0 0 0 0 X X X X X X C P O LC P H AWr i te C P O L, C P H A contr ol
b i ts. S ee Tab l e 15.
DIN 1 1 0 0 0 0 0 1 X X X X X X X X
DOUTRB X X X X X X X X X X X X X X C P O LC P H A
Read C P OL, C P H A contr ol
b i ts.
Table 2b. Advanced-Feature Programming Commands (continued)
X = Don’t care.
Buffered, Fast-Settling, Voltage-Output DAGs Octal, 12/10/8-Bit, E 5 E: s 3; 57%; g S x uvm >< ugm="" mam="" cam="" cam="">< uacn="" cur/cu="">< cum="" e="" 7="" wm="" 7="" am="" am="" mm="" mm="" 7="" hm="" 9m="" 7="" 77m="" e="" 7="" m="" 7="" m="" 63m="" 2am="" 23m="" 7="" m="" zmw="" 7="" zmw="" e="" 7="" :vm="" 7="" tam="" :me="" {am="" {am="" 7="" mm="" mm="" 7="" mm="" 3="" 7="" «wm="" 7="" am="" «am="" mm="" m="" 7="" w="" mm="" 7="" w="" e="" 7="" m="" 7="" 59m="" 53m="" sum="" in="" 7="" each="" 59m="" 7="" smw="" e="" 7="" am="" 7="" 99m="" 93m="" 9am="" 93m="" 7="" am="" am="" 7="" sm\="" e="" 7="" 77m="" 7="" 79m="" 7mm="" 1mm="" 13m="" 7="" lac“="" 79m="" 7="" 17m="" e="" 7="" mm="" 7="" 89m="" mm="" mm="" 23m="" 7="" am="" 890‘="" 7="" nm="" e="" 7="" svm="" 7="" 59m="" 53m="" saw="" an="" 7="" m="" and="" 7="" 67m="" e="" 7="" mm="" 7="" xacn="" mm="" ham="" ham="" 7="" hm="" mm="" 7="" mm="" gg="" 7="" 1mm="" 7="" yaacl="" mm="" mm="" 300="" 7="" man="" man="" 7="" man="" 5="" 7="" 9mm="" 7="" esau="" ema="" mg="" mg="" 7="" gm="" 952cm="" 7="" ma="" e="" 7="" emma="" 7="" mam/j="" mm="" a="" m="" mam/j="" 7="" mm="" mnau="" 7="" mhua="" g="" 7="" two="" 7="" ham="" ham="" mag="" 13cm="" 7="" hum="" mm="" 7="" mm="" g="" a="">< 7="" 7="">< 7="" 7="" 7="" x="" 7="" 7="" 7="" g;="" 7="" c="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" t:="" 32"="" 7="" 7,="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" eeev="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" §%gg="" 7="" 7,="" 7="" 7="" 7="" 7="" 7="" 7="" 7,="" 7="" say="" x="" ,="" 7="" x="" 7="" 7="" x="" 7="" ,="" 7="" 85:7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" 7="" a="" l="" a="" a="" d="" a="" a="" [vi/jxiiiii="">
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
22 ______________________________________________________________________________________
CONTROL BITS DATA BITS
DATA C3 C2 C1 C0 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
READ INPUT AND DAC REGISTERS A–H
DIN 1101000X 1 1 1111111111 1 111XX XXXXXX
DOUTRB X X X X X X X X
DDA_11
DDA_10
DDA_9
DDA_8
DDA_7
DDA_6
DDA_5
DDA_4
DDA_3
DDA_2
DDA_1
DDA_0
IDA_11
IDA_10
IDA_9
IDA_8
IDA_7
IDA_6
IDA_5
IDA_4
IDA_3
IDA_2
IDA_1
IDA_0
Read input
register A and
DAC register A
(all 24 bits).**†
DIN 1101001X 1 1 1111111111 1 111XX XXXXXX
DOUTRB X X X X X X X X
DDB_11
DDB_10
DDB_9
DDB_8
DDB_7
DDB_6
DDB_5
DDB_4
DDB_3
DDB_2
DDB_1
DDB_0
IDB_11
IDB_10
IDB_9
IDB_8
IDB_7
IDB_6
IDB_5
IDB_4
IDB_3
IDB_2
IDB_1
IDB_0
Read input
register B and
DAC register B
(all 24 bits).**†
DIN 1101010X 1 1 1111111111 1 111XX XXXXXX
DOUTRB X X X X X X X X
DDC_11
DDC_10
DDC_9
DDC_8
DDC_7
DDC_6
DDC_5
DDC_4
DDC_3
DDC_2
DDC_1
DDC_0
IDC_11
IDC_10
IDC_9
IDC_8
IDC_7
IDC_6
IDC_5
IDC_4
IDC_3
IDC_2
IDC_1
IDC_0
Read input
register C and
DAC register C
(all 24 bits).**†
DIN 1101011X 1 1 1111111111 1 111XX XXXXXX
DOUTRB X X X X X X X X
DDD_11
DDD_10
DDD_9
DDD_8
DDD_7
DDD_6
DDD_5
DDD_4
DDD_3
DDD_2
DDD_1
DDD_0
IDD_11
IDD_10
IDD_9
IDD_8
IDD_7
IDD_6
IDD_5
IDD_4
IDD_3
IDD_2
IDD_1
IDD_0
Read input
register D and
DAC register D
(all 24 bits).**†
DIN 1101100X 1 1 1111111111 1 111XX XXXXXX
DOUTRB X X X X X X X X
DDE_11
DDE_10
DDE_9
DDE_8
DDE_7
DDE_6
DDE_5
DDE_4
DDE_3
DDE_2
DDE_1
DDE_0
IDE_11
IDE_10
IDE_9
IDE_8
IDE_7
IDE_6
IDE_5
IDE_4
IDE_3
IDE_2
IDE_1
IDE_0
Read input
register E and
DAC register E
(all 24 bits).**†
DIN 1101101X 1 1 1111111111 1 111XX XXXXXX
DOUTRB X X X X X X X X
DDF_11
DDF_10
DDF_9
DDF_8
DDF_7
DDF_6
DDF_5
DDF_4
DDF_3
DDF_2
DDF_1
DDF_0
IDF_11
IDF_10
IDF_9
IDF_8
IDF_7
IDF_6
IDF_5
IDF_4
IDF_3
IDF_2
IDF_1
IDF_0
Read input
register F and
DAC register F
(all 24 bits).**†
DIN 1101110X 1 1 1111111111 1 111XX XXXXXX
DOUTRB X X X X X X X X
DDG_11
DDG_10
DDG_9
DDG_8
DDG_7
DDG_6
DDG_5
DDG_4
DDG_3
DDG_2
DDG_1
DDG_0
IDG_11
IDG_10
IDG_9
IDG_8
IDG_7
IDG_6
IDG_5
IDG_4
IDG_3
IDG_2
IDG_1
IDG_0
Read input
register G and
DAC register G
(all 24 bits).**†
DIN 1101111X 1 1 1111111111 1 111XX XXXXXX
DOUTRB X X X X X X X X
DDH_11
DDH_10
DDH_9
DDH_8
DDH_7
DDH_6
DDH_5
DDH_4
DDH_3
DDH_2
DDH_1
DDH_0
IDH_11
IDH_10
IDH_9
IDH_8
IDH_7
IDH_6
IDH_5
IDH_4
IDH_3
IDH_2
IDH_1
IDH_0
Read input
register H and
DAC register H
(all 24 bits).**†
Table 2c. 24-Bit Read Commands
X = Don’t care.
**
D23–D12 represent the 12-bit data from the corresponding DAC register. D11–D0 represent the 12-bit data from the corresponding input register. For
the MAX5592/MAX5593, bits D13, D12, D1, and D0 are zero bits. For the MAX5594/MAX5595, bits D15–D12 and D3–D0 are zero bits.
†
During readback, all ones (code FF) must be clocked into DIN for all 24 bits. No command can be issued before all 24 bits have been clocked out.
CS must be kept low while all 24 bits are being clocked out.
lVI/JXI [VI
MAX5590–MAX5595
DAC Programming Examples:
To load input register A from the shift register, leaving
DAC register A unchanged (DAC output unchanged),
use the command in Table 3.
The MAX5590–MAX5595 can load all of the input regis-
ters (A–H) simultaneously from the shift register, leaving
the DAC registers unchanged (DAC output unchanged),
by using the command in Table 4.
To load all of the input registers (A–H) and all of the DAC
registers (A–H) simultaneously, use the command in
Table 5.
For the 10-bit and 8-bit versions, set sub-bits = 0 for
best performance.
Advanced-Feature
Programming Commands
Select Bits (M_)
The select bits allow synchronous updating of any com-
bination of channels. The select bits command the
loading of the DAC register from the input register of
each channel. Set the select bit M_ = 1 to load the DAC
register “_” with data from the input register “_”, where
“_” is replaced with A, B, or C and so on through H,
depending on the selected channel. Setting the select
bit M_ = 0 results in no action for that channel (Table 6).
Select Bits Programming Example:
To load DAC register B from input register B while
keeping other channels (A, C–H) unchanged, set MB =
1 and M_ = 0 (Table 7).
Table 3. Load Input Register A from Shift Register
Table 4. Load Input Registers (A–H) from Shift Register
Table 5. Load Input Registers (A–H) and DAC Registers (A–H) from Shift Register
Table 6. Select Bits (M_)
DATA CONTROL BITS DATA BITS
DIN 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0
DATA CONTROL BITS DATA BITS
DIN 1 0 0 1 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0
DATA CONTROL BITS DATA BITS
DIN 1 0 1 0 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0
DATA CONTROL BITS DATA BITS
DIN1000XXXXMHMGMFMEMDMCMBMA
Table 7. Select Bits Programming Example
DATA CONTROL BITS DATA BITS
DIN1000XX0000000010
X = Don’t care.
X = Don’t care.
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 23
[VIIJXIIVI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
24 ______________________________________________________________________________________
Table 9. Shutdown-Mode Write Command (DACA–DACD)
Table 10. Shutdown-Mode Write Command (DACE–DACH)
Table 11. Shutdown-Control-Bits Write Command
DATA CONTROL BITS DATA BITS
DIN10110000P D D 1P D D 0P D C 1P D C 0P D B1 P D B0 P D A1 P D A0
DATA CONTROL BITS DATA BITS
DIN10110010P D H 1P D H 0P D G 1P D G 0P D F1 P D F0 P D E 1P D E 0
DATA CONTROL BITS DATA BITS
DIN10110100P D C H P D C GP D C FP D C E P D C D P D C C P D C BP D C A
X = Don’t care.
X = Don’t care.
Table 12. Settling-Time-Mode Write Command
DATA CONTROL BITS DATA BITS
DIN10111000S P D H S P D GS P D FS P D E S P D D S P D C S P D BS P D A
X = Don’t care.
Shutdown-Mode Bits (PD_0, PD_1)
Use the shutdown-mode bits and control bits to
shut down each DAC independently. The shutdown-
mode bits determine the output state of the selected
channels. The shutdown-control bits put the selected
channels into shutdown-mode. To select the shutdown
mode for DACA–DACH, set PD_0 and PD_1 according
to Table 8 (where “_” is replaced with one of the select-
ed channels (A–H)). The three possible states for unity-
gain versions are 1) normal operation, 2) shutdown with
1kΩoutput impedance, and 3) shutdown with 100kΩ
output impedance. The three possible states for force-
sense versions are 1) normal operation, 2) shutdown
with 1kΩoutput impedance, and 3) shutdown with the
output in a high-impedance state. Tables 9 and 10
show the commands for writing to the shutdown-mode
bits. Table 11 shows the commands for writing the
shutdown-control bits. This command is required to put
the selected channels into shutdown.
Always write the shutdown-mode-bits command first
and then write the shutdown-control-bits command to
properly shut down the selected channels. The shut-
down-control-bits command can be written at any time
after the shutdown-mode-bits command. It does not
have to immediately follow the shutdown-mode-bits
command.
Settling-Time-Mode Bits (SPD_)
The settling-time-mode bits select the settling time (FAST
mode or SLOW mode) of the MAX5590–MAX5595.
Set SPD_ = 1 to select FAST mode or set SPD_ = 0 to
select SLOW mode, where “_” is replaced by A, B, or C
and so on through H, depending on the selected chan-
nel (Table 12). FAST mode provides a 3µs maximum set-
tling time, and SLOW mode provides a 6µs maximum
settling time.
Table 8. Shutdown-Mode Bits
PD_1 PD_0 DESCRIPTIONS
00
Shutdown with 1kΩ termination to ground
on DAC_ output.
01
Shutdown with 100kΩ termination to
ground on DAC_ output for unity-gain
versions. Shutdown with high-impedance
output for force-sense versions.
1 0 Ignored.
11
DAC_ is powered up in its normal
operating mode.
lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 25
Settling-Time-Mode Write Example:
To configure DACA and DACD into FAST mode and
DACB and DACC into SLOW mode, use the command
in Table 13.
To read back the settling-time-mode bits, use the com-
mand in Table 14.
CPOL and CPHA Control Bits
The CPOL and CPHA control bits of the
MAX5590–MAX5595 are defined the same as the CPOL
and CPHA bits in the SPI standard. Set the DAC’s
CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or
CPOL = 1 and CPHA = 1 for MICROWIRE and SPI
applications requiring the clocking of data in on the ris-
ing edge of SCLK. Set the DAC’s CPOL and CPHA bits
to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA =
0 for DSP and SPI applications, requiring the clocking
of data in on the falling edge of SCLK (refer to the
Programmer’s Handbook
and see Table 15 for details).
At power-up, if DSP = DVDD, the default value of CPHA
is zero and if DSP = DGND, the default value of CPHA
is one. The default value of CPOL is zero at power-up.
To write to the CPOL and CPHA bits, use the command
in Table 16.
To read back the device’s CPOL and CPHA bits, use
the command in Table 17.
Table 13. Settling-Time-Mode Write Example
DATA CONTROL BITS DATA BITS
DIN10111000XXXX1001
X = Don’t care.
Table 14. Settling-Time-Mode Read Command
DATA CONTROL BITS DATA BITS
DIN10111001XXXXXXXX
D OU TRBXXXXXXXXS P D H S P D GS P D FS P D E S P D D S P D C S P D BS P D A
Table 17. CPOL and CPHA Read Command
DATA CONTROL BITS DATA BITS
DIN 1 1 0 0 0 0 0 1 X X X X X X X X
D OU TRBXXX X XXX XXXXX XXC P O LC P H A
Table 15. CPOL and CPHA Bits
CPOL CPHA DESCRIPTION
00
Default values at power-up when DSP is connected to DVDD. Data is clocked in on the rising edge
of SCLK.
01
Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge
of SCLK.
1 0 Data is clocked in on the falling edge of SCLK.
1 1 Data is clocked in on the rising edge of SCLK.
Table 16. CPOL and CPHA Write Command
DATA CONTROL BITS DATA BITS
DIN11000000XXXXXXC P O LC P H A
X = Don’t care.
X = Don’t care.
X = Don’t care.
[VIIJXIIVI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
26 ______________________________________________________________________________________
Table 20. UPIO Programming Example
DATA CONTROL BITS DATA BITS
DIN10110110010000XX
X = Don’t care.
Table 21. UPIO Read Command
DATA CONTROL BITS DATA BITS
DIN10110111XXXXXXXX
DOUTRB X X XXXXXXU P 3- 2U P 2- 2U P 1- 2U P 0- 2U P 3- 1U P 2- 1U P 1- 1U P 0- 1
X = Don’t care.
UPIO Bits (UPSL1, UPSL2, UP0–UP3)
The MAX5590–MAX5595 provide two user-programma-
ble input/output (UPIO) ports: UPIO1 and UPIO2. These
ports have 15 possible configurations, as shown in
Table 22. UPIO1 and UPIO2 can be programmed inde-
pendently or simultaneously by writing to the UPSL1,
UPSL2, and UP0–UP3 bits (Table 18).
Table 19 shows how UPIO1 and UPIO2 are selected for
configuration. The UP0–UP3 bits select the desired
functions for UPIO1 and/or UPIO2 (Table 22).
UPIO Programming Example:
To set only UPIO1 as LDAC and leave UPIO2
unchanged, use the command in Table 20.
The UPIO selection and configuration bits can be read
back from the MAX5590–MAX5595 when UPIO1 or
UPIO2 is configured as a DOUTRB output. Table 21
shows the read-back data format for the UPIO bits.
Writing the command in Table 21 initiates a read opera-
tion of the UPIO bits. The data is clocked out starting on
the ninth clock cycle of the sequence. Bits UP3-2
through UP0-2 provide the UP3–UP0 configuration bits
for UPIO2 (Table 22), and bits UP3-1 through UP0-1
provide the UP3–UP0 configuration bits for UPIO1.
Table 18. UPIO Write Command
DATA CONTROL BITS DATA BITS
DIN10110110U P S L2 U P S L1 UP3 UP2 UP1 UP0 X X
X = Don’t care.
Table 19. UPIO Selection Bits (UPSL1 and UPSL2)
UPSL2 UPSL1 UPIO PORT SELECTED
0 0 None selected
0 1 UPIO1 selected
1 0 UPIO2 selected
1 1 Both UPIO1 and UPIO2 selected
lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 27
UPIO Configuration
Table 22 lists the possible configurations for UPIO1 and
UPIO2. UPIO1 and UPIO2 use the selected function
when configured by the UP3–UP0 configuration bits.
LDAC
LDAC controls the loading of the DAC registers. When
LDAC is high, the DAC registers are latched, and any
change in the input registers does not affect the con-
tents of the DAC registers or the DAC outputs. When
LDAC is low, the DAC registers are transparent, and the
values stored in the input registers are fed directly to the
DAC registers, and the DAC outputs are updated.
Drive LDAC low to asynchronously load the DAC regis-
ters from their corresponding input registers (DACs that
are in shutdown remain shut down). The LDAC input
does not require any activity on CS, SCLK, or DIN to
take effect. If LDAC is brought low coincident with a ris-
ing edge of CS (which executes a serial command
modifying the value of either DAC input register), then
LDAC must remain asserted for at least 120ns following
the CS rising edge. This requirement applies only for
serial commands that modify the value of the DAC input
registers. See Figures 5 and 6 for timing details.
Table 22. UPIO Configuration Register Bits (UP3–UP0)
UPIO CONFIGURATION BITS
UP3 UP2 UP1 UP0 FUNCTION DESCRIPTION
0000 LDAC Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers
with data from input registers.
0001 SET Active-Low Input. Drive low to set all input and DAC registers to full scale.
0010 MID Active-Low Input. Drive low to set all input and DAC registers to midscale.
0011 CLR Active-Low Input. Drive low to set all input and DAC registers to zero scale.
0100 PDL Active-Low Power-Down Lockout Input. Drive low to disable software shutdown.
0101Reserved This mode is reserved. Do not use.
0110SHDN1K
Active-Low 1kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the
MAX5590/MAX5592/MAX5594, drive SHDN1K low to pull OUTA–OUTH to AGND
with 1kΩ. For the MAX5591/MAX5593/MAX5595, drive SHDN1K low to leave
OUTA–OUTH high impedance.
0111SHDN100K
Active-Low 100kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the
MAX5590/MAX5592/MAX5594, drive SHDN100K low to pull OUTA–OUTH to
AGND with 100kΩ. For the MAX5591/MAX5593/MAX5595, drive low to leave
OUTA–OUTH high impedance.
1000DOUTRB Data Read-Back Output
1001DOUTDC0 Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of
1010DOUTDC1 Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK.
1011 GPIGeneral-Purpose Logic Input
1100 GPOLGeneral-Purpose Logic-Low Output
1101GPOH General-Purpose Logic-High Output
1110TOGG
Toggle Input. Toggles DAC outputs between data in input registers and data in
DAC registers. Drive low to set all DAC outputs to values stored in input registers.
Drive high to set all DAC outputs to values stored in DAC registers.
1111 FAST Fast/Slow Settling-Time-Mode Input. Drive low to select FAST (3µs) mode or drive
high to select SLOW (6µs) settling mode. Overrides the SPDA–SPDH settings.
[VIIJXIIVI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
28 ______________________________________________________________________________________
SET, MID, CLR
The SET, MID, and CLR signals force the DAC outputs
to full scale, midscale, or zero scale (Figure 5). These
signals cannot be active at the same time.
The active-low SET input forces the DAC outputs to full
scale when SET is low. When SET is high, the DAC out-
puts follow the data in the DAC registers.
The active-low MID input forces the DAC outputs to
midscale when MID is low. When MID is high, the DAC
outputs follow the data in the DAC registers.
The active-low CLR input forces the DAC outputs to
zero scale when CLR is low. When CLR is high, the
DAC outputs follow the data in the DAC registers.
If CLR, MID, or SET signals go low during a write com-
mand, reload the data to ensure accurate results.
Power-Down Lockout (PDL)
The PDL active-low, software-shutdown lockout input
overrides (not overwrites) the PD_0 and PD_1 shutdown-
mode bits. PDL cannot be active at the same time as
SHDN1K or SHDN100K (see the
Shutdown Mode
(SHDN1K, SHDN100K)
section).
If the PD_0 and PD_1 bits command the DAC to
shut down prior to PDL going low, the DAC returns to
shutdown mode immediately after PDL goes high,
unless the PD_0 and PD_1 bits were modified through
the serial interface in the meantime.
Shutdown Mode (SSHHDDNN11KK, SSHHDDNN110000KK)
The SHDN1K and SHDN100K are active-low signals
that override (not overwrite) the PD_1 and PD_0 bit set-
tings. For the MAX5590/MAX5592/MAX5594, drive
SHDN1K low to select shutdown mode with OUTA–
OUTH internally terminated with 1kΩto ground, or drive
SHDN100K low to select shutdown with an internal
100kΩtermination. For the MAX5591/MAX5593/
MAX5595, drive SHDN1K low for shutdown with 1kΩ
output termination, or drive SHDN100K low for shut-
down with high-impedance outputs.
For proper shutdown, first select a shutdown mode
(Table 8), then use the shutdown-control bits as listed
in Table 2b.
Data Output (DOUTRB, DOUTDC0, DOUTDC1)
UPIO1 and UPIO2 can be configured as serial data out-
puts, DOUTRB (data out for read back), DOUTDC0
(data out for daisy-chaining, mode 0), and DOUTDC1
(data out for daisy-chaining, mode 1). The differences
between DOUTRB and DOUTDC0 (or DOUTDC1) are
as follows:
• The source of read-back data on DOUTRB is the
DOUT register. Daisy-chain DOUTDC_ data comes
directly from the shift register.
• Read-back data on DOUTRB is only present after a
DAC read command. Daisy-chain data is present on
DOUTDC_ for any DAC write after the first 16 bits
are written.
• The DOUTRB idle state (CS = high) for read back is
high impedance. Daisy-chain DOUTDC_ idles high
when inactive to avoid floating the data input in the
next device in the daisy-chain.
See Figures 1 and 2 for timing details.
tGP
tLDS
END OF
CYCLE*
GPO_
LDAC
* END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH
ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION.
tCMS
tLDL
tS±0.5 LSB
TOGG
VOUT_
LDAC
PDL
CLR,
MID, OR
SET
PDL AFFECTS DAC OUPTUTS (VOUT_) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN.
Figure 5. Asynchronous Signal Timing Figure 6. GPO_ and LDAC Signal Timing
[MAXI/VI lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 29
GPI, GPOL, GPOH
UPIO1 and UPIO2 can each be configured as a gener-
al-purpose input (GPI), a general-purpose output low
(GPOL), or a general-purpose output high (GPOH).
The GPI can serve to detect interrupts from µPs or micro-
controllers. The GPI has three functions:
1) Sample the signal at GPI at the time of the read
(RTP1 and RTP2).
2) Detect whether or not a falling edge has occurred
since the last read or reset (LF1 and LF2).
3) Detect whether or not a rising edge has occurred
since the last read or reset (LR1 and LR2).
RTP1, LF1, and LR1 represent the data read from
UPIO1; RTP2, LF2, and LR2 represent the data read
from UPIO2.
To issue a read command for the UPIO configured as
GPI, use the command in Table 23.
Once the command is issued, RTP1 and RTP2 provide
the real-time status (0 or 1) of the inputs at UPIO1 or
UPIO2, respectively, at the time of the read. If LF2 or
LF1 is one, then a falling edge has occurred on the
respective UPIO1 or UPIO2 input since the last read or
reset. If LR2 or LR1 is one, then a rising edge has
occurred since the last read or reset.
GPOL outputs a constant low, and GPOH outputs a
constant high. See Figure 6.
TOGG
Use the TOGG input to toggle the DAC outputs
between the values in the input registers and DAC reg-
isters. A delay of greater than 100ns from the end of the
previous write command is required before the TOGG
signal can be correctly switched between the new
value and the previously stored value. When TOGG =
0, the output follows the information in the input regis-
ters. When TOGG = 1, the output follows the informa-
tion in the DAC register (Figure 5).
FAST
The MAX5590–MAX5595 have two settling-time-mode
options: FAST (3µs max) and SLOW (6µs max). To
select the FAST mode, drive FAST low, and to select
SLOW mode, drive FAST high. This overrides (not over-
writes) the SPDA–SPDH bit settings.
Table 23. GPI Read Command
DATA CONTROL BITS DATA BITS
DIN1011101XXXXXXXXX
DOUTRB X X XXXXXXXXRTP2 LF2 LR2 RTP1 LF1 LR1
Table 24. Unipolar Code Table (Gain = +1)
DAC CONTENTS
MSB LSB ANALOG OUTPUT
1111 1111 1111 +VREF (4095 / 4096)
1000 0000 0001 +VREF (2049 / 4096)
1000 0000 0000 +VREF (2048 / 4096) = VREF / 2
0111 1111 1111 +VREF (2047 / 4096)
0000 0000 0001 +VREF (1 / 4096)
0000 0000 0000 0
MAX5590
DAC_
REF_
OUT_
VOUT_ = VREF_ x CODE / 4096
CODE IS THE DAC_ INPUT
CODE (0 TO 4095 DECIMAL).
Figure 7. Unipolar Output Circuit
X = Don’t care.
m lVl/lxl/Vl [Ill IIXI [Ill [VIIJXIIVI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
30 ______________________________________________________________________________________
Applications Information
Unipolar Output
Figure 7 shows the unity-gain MAX5590 in a unipolar
output configuration. Table 24 lists the unipolar out-
put codes.
Bipolar Output
The MAX5590 outputs can be configured for bipolar
operation, as shown in Figure 8. The output voltage is
given by the following equation:
VOUT_ = VREF x (CODE - 2048) / 2048
where CODE represents the numeric value of the
DAC’s binary input code (0 to 4095 decimal). Table 25
shows digital codes and the corresponding output volt-
age for the Figure 8 circuit.
Configurable Output Gain
The MAX5591/MAX5593/MAX5595 have force-sense
outputs, which provide a direct connection to the invert-
ing terminal of the output op amp, yielding the most
flexibility. The force-sense output has the advantage
that specific gains can be set externally for a given
application. The gain error for the MAX5591/MAX5593/
MAX5595 is specified in a unity-gain configuration (op-
amp output and inverting terminals connected), and
additional gain error results from external resistor
tolerances. The force-sense DACs allow many useful
circuits to be created with only a few simple external
components.
An example of a custom, fixed gain using the
MAX5591’s force-sense output is shown in Figure 9. In
this example, the external reference is set to 1.25V, and
the gain is set to +1.1V/V with external discrete resis-
tors to provide an approximate 0 to 1.375V DAC output
voltage range.
VOUT = [(0.5 x VREF_ x CODE) / 4096] x [1 + (R2 / R1)]
where CODE represents the numeric value of the
DAC’s binary input code (0 to 4095 decimal).
In this example, R2 = 12kΩand R1 = 10kΩto set the
gain = 1.1V/V.
VOUT = [(0.5 x 1.25V x CODE) / 4096] x 2.2
Table 25. Bipolar Code Table (Gain = +1)
DAC CONTENTS
MSB LSB ANALOG OUTPUT
1111 1111 1111 +VREF (2047 / 2048)
1000 0000 0001 +VREF (1 / 2048)
1000 0000 0000 0
0111 1111 1111 -VREF (1 / 2048)
0000 0000 0001 -VREF (2047 / 2048)
0000 0000 0000 -VREF (2048 / 2048) = -VREF
Figure 8. Bipolar Output Circuit
MAX5590
DAC_
REF OUT_
10kΩ10kΩ
V+
V-
VOUT
MAX5591
DAC_
REF
OUT_
FB_
R2 = 12kΩ
0.1%
25ppm
R1 = 10kΩ
0.1%
25ppm
Figure 9. Configurable Output Gain
MAXIM lVI/JXI [VI
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 31
Power-Supply and Layout Considerations
Bypass the analog and digital power supplies by using a
10µF capacitor in parallel with a 0.1µF capacitor to AGND
and DGND (Figure 10). Minimize lead lengths to reduce
lead inductance. Use shielding and/or ferrite beads to fur-
ther increase isolation.
Digital and AC transient signals coupling to AGND can
create noise at the output. Connect AGND to the high-
est quality ground available. Use proper grounding
techniques, such as a multilayer board with a low-
inductance ground plane. Wire-wrapped boards and
sockets are not recommended. For optimum system
performance, use PC boards with separate analog and
digital ground planes. Connect the two ground planes
together at the low-impedance power-supply source.
Using separate power supplies for AVDD and DVDD
improves noise immunity. Connect AGND and DGND at
the low-impedance power-supply sources (Figure 11).
MAX5590–MAX5595
VREF
10µF* 0.1µF*
REF
SCLK
DIN
PU
UPIO1
UPIO2
CS
DSP
AGND** DGND**
OUTA
FBA
FBH
OUTH
MAX5591
MAX5593
MAX5595
ONLY
10µF0.1µF10µF0.1µF
DVDD
AVDD
DVDD
AVDD
*REMOVE BYPASS CAPACITORS ON REF FOR AC-REFERENCE INPUTS.
**CONNECT ANALOG AND DIGITAL GROUND PLANES AT THE
LOW-IMPEDANCE POWER-SUPPLY SOURCE.
Figure 10. Bypassing Power Supplies AV
DD
, DV
DD
, and REF
MAX5590–MAX5595
0.1µF
10µF
AVDD AGND
AVDD AGND
0.1µF
10µF
DVDD DGND
DVDD DGND
DVDD DGND
ANALOG SUPPLY DIGITAL SUPPLY
DIGITAL
CIRCUITRY
Figure 11. Separate Analog and Digital Power Supplies
MAX5590—MAX55 32 TDPV‘EW l: j M” E E W AGND 2 :‘ AGND E E PU mm 3 :‘ OUTA E Z] UUTH m 4 :I NE E MAXIM Z1 NC m 5 MAXIM j ours 5 MAX55917 20 we E MAX559Z 3 WW 6 3 WC E MAX5594 E 0W we 7 3 mm: E E 0qu m a :l N: E E N C FBD 9 :l as a E mm mm m :‘ SCLK E E Wm R E :‘ DW H E DGND SW E :l m ‘2 E Wm] M E j TssoP W E :‘ PROCESS B‘C to www.maxim-ic.cam/gackages 21 43066 21 43066 [VI/JXIIIII
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
32 ______________________________________________________________________________________
Chip Information
PROCESS: BiCMOS
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
REF
PU
OUTH
N.C.N.C.
OUTA
AGND
AVDD
TOP VIEW
OUTG
OUTF
OUTE
N.C.N.C.
OUTD
OUTC
OUTB
16
15
14
13
9
10
11
12
UPIO2
UPIO1
DGND
DVDD
DSP
DIN
SCLK
CS
TSSOP
MAX5590
MAX5592
MAX5594
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
REF
PU
OUTH
FBH
FBG
OUTG
DVDD
OUTF
FBF
FBE
OUTE
UPIO2
UPIO1
DGND
DSP
DIN
SCLK
CS
OUTD
FBD
FBC
OUTC
OUTB
FBB
FBA
OUTA
AGND
AVDD
TSSOP
MAX5591
MAX5593
MAX5595
+
+
Pin Configurations
Selector Guide
PART
OUTPUT
BUFFER
CO NFIGUR ATION
R ESO L U TIO N
( B IT S)
INL
(LSBs
MAX)
MAX5590AEUG+ Unity Gain 12 ±1
MAX5590BEUG+ Unity Gain 12 ±4
MAX5591AEUI+ Force Sense 12 ±1
MAX5591BEUI+ Force Sense 12 ±4
MAX5592EUG+ Unity Gain 10 ±1
MAX5593EUI+ Force Sense 10 ±1
MAX5594EUG+ Unity Gain 8 ±0.5
MAX5595EUI+ Force Sense 8 ±0.5
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
24 TSSOP U24+1 21-0066
28 TSSOP U28+2 21-0066
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
33
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
2 7/07 Updated EC table specifications 1, 6–9, 33
3 1/10 Added lead-free information and amended data sheet 1–13, 16, 20,
32, 33

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