XC866 Datasheet by Infineon Technologies

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Microcontrollers

Data Sheet, V1.2, Oct. 2007

XC866

8-Bit Single-Chip Microcontroller

Edition 2007-10

Published by Infineon Technologies AG,

81726 München, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values

stated herein and/or any information regarding the application of the device, Infineon Technologies hereby

disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-

infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

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Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

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(Infineon Never stop thinking

Microcontrollers

Data Sheet, V1.2, Oct. 2007

XC866

8-Bit Single-Chip Microcontroller

XC866 Data Sheet

Revision History: 2007-10 V1.2

Previous Version: V 0.1, 2005-01

V1.0, 2006-02

V1.1, 2006-12

Page Subjects (major changes since last revision)

3Device summary table is updated for Flash 4-Kb and ROM variants.

13 Footnote is added to MBC pin; description of VDDP pin is updated.

25 Section on bit protection scheme and access type of register bit field

PASSWD.PASS are updated.

26 Access type of PAGE bits of all module page registers are corrected to rwh.

29 Access type of Px_DIR register bits are corrected to rwh

38 New bullet point on Flash delivery state is added to the feature list.

88 Digital power supply voltage are differentiated for 5V and 3.3V variants.

89 New parameters on XTAL1 hysteresis and Voltage on GPIO pins during

VDDP power-off condition are added.

104 Figure on Power-on reset timing is updated.

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

mcdocu.comments@infineon.com

(iﬁneon

Data Sheet 1 V1.2, 2007-10

XC8668-Bit Single-Chip Microcontroller

XC800 Family

1 Summary of Features

• High-performance XC800 Core

– compatible with standard 8051 processor

– two clocks per machine cycle architecture (for memory access without wait state)

– two data pointers

• On-chip memory

– 8 Kbytes of Boot ROM

– 256 bytes of RAM

– 512 bytes of XRAM

– 4/8/16 Kbytes of Flash; or

8/16 Kbytes of ROM, with additional 4 Kbytes of Flash

(includes memory protection strategy)

• I/O port supply at 3.3 V/5.0 V and core logic supply at 2.5 V (generated by embedded

voltage regulator)

(further features are on next page)

Figure 1 XC866 Functional Units

Port 0

Port 1

Port 2

Port 3

XC800 Core

UART

ADC

10-bit

8-channel

Boot ROM

8K Bytes

XRAM

512 Bytes

RAM

256 Bytes

On-Chip Debug Support

Timer 0

16-bit

Timer 1

16-bit

Timer 2

16-bit

Watchdog

Timer

SSC

4K/ 8K/16K Bytes Flash

or 8K/16K Bytes ROM

Capture/Com pare Unit

16-bit

Com pare Unit

16-bit

6-bit Digital I/O

5-bit Digital I/O

8-bit Digital I/O

8-bit Digital/Analog Input

1) All ROM devices include 4K bytes Flash

,/ Infineon

XC866

Summary of Features

Data Sheet 2 V1.2, 2007-10

Features (continued):

• Reset generation

– Power-On reset

– Hardware reset

– Brownout reset for core logic supply

– Watchdog timer reset

– Power-Down Wake-up reset

• On-chip OSC and PLL for clock generation

– PLL loss-of-lock detection

• Power saving modes

– slow-down mode

– idle mode

– power-down mode with wake-up capability via RXD or EXINT0

– clock gating control to each peripheral

• Programmable 16-bit Watchdog Timer (WDT)

• Four ports

– 19 pins as digital I/O

– 8 pins as digital/analog input

• 8-channel, 10-bit ADC

• Three 16-bit timers

– Timer 0 and Timer 1 (T0 and T1)

–Timer 2

• Capture/compare unit for PWM signal generation (CCU6)

• Full-duplex serial interface (UART)

• Synchronous serial channel (SSC)

• On-chip debug support

– 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM)

– 64 bytes of monitor RAM

• PG-TSSOP-38 pin package

• Temperature range TA:

– SAF (-40 to 85 °C)

– SAK (-40 to 125 °C)

Inflneon

XC866

Summary of Features

Data Sheet 3 V1.2, 2007-10

XC866 Variant Devices

The XC866 product family features devices with different configurations and program

memory sizes, temperature and quality profiles (Automotive or Industrial), offering cost-

effective solution for different application requirements.

The configuration of LIN BSL for XC866 devices are summarized in Table 1.

The list of XC866 devices and their differences are summarized in Table 2.

Table 1 Device Configuration for LIN BSL

Device Name LIN BSL Support

XC866 No

XC866L Yes

Table 2 Device Summary

Device

Type

Device Name Power

Supply

(V)

P-Flash

Size

(Kbytes)

D-Flash

Size

(Kbytes)

ROM

Size

(Kbytes)

Quality

Profile1)

Flash2) SAK-XC866*-4FRA 5.0 12 4 – Automotive

SAK-XC866*-4FRI 5.0 12 4 – Industrial

SAK-XC866*-2FRA 5.0 4 4 – Automotive

SAK-XC866*-2FRI 5.0 4 4 – Industrial

SAK-XC866*-1FRA 5.0 – 4 – Automotive

SAK-XC866*-1FRI 5.0 – 4 – Industrial

SAF-XC866*-4FRA 5.0 12 4 – Automotive

SAF-XC866*-4FRI 5.0 12 4 – Industrial

SAF-XC866*-2FRA 5.0 4 4 – Automotive

SAF-XC866*-2FRI 5.0 4 4 – Industrial

SAF-XC866*-1FRA 5.0 – 4 – Automotive

SAF-XC866*-1FRI 5.0 – 4 – Industrial

SAK-XC866*-4FRA 3V 3.3 12 4 – Automotive

SAK-XC866*-4FRI 3V 3.3 12 4 – Industrial

SAK-XC866*-2FRA 3V 3.3 4 4 – Automotive

SAK-XC866*-2FRI 3V 3.3 4 4 – Industrial

SAK-XC866*-1FRA 3V 3.3 – 4 – Automotive

n/ Infineon

XC866

Summary of Features

Data Sheet 4 V1.2, 2007-10

Note: The asterisk (*) above denotes the device configuration letters from Table 1.

SAK-XC866*-1FRI 3V 3.3 – 4 – Industrial

SAF-XC866*-4FRA 3V 3.3 12 4 – Automotive

SAF-XC866*-4FRI 3V 3.3 12 4 – Industrial

SAF-XC866*-2FRA 3V 3.3 4 4 – Automotive

SAF-XC866*-2FRI 3V 3.3 4 4 – Industrial

SAF-XC866*-1FRA 3V 3.3 – 4 – Automotive

SAF-XC866*-1FRI 3V 3.3 – 4 – Industrial

ROM SAK-XC866*-4RRA 5.0 – 4 16 Automotive

SAK-XC866*-4RRI 5.0 – 4 16 Industrial

SAK-XC866*-2RRA 5.0 – 4 8 Automotive

SAK-XC866*-2RRI 5.0 – 4 8 Industrial

SAF-XC866*-4RRA 5.0 – 4 16 Automotive

SAF-XC866*-4RRI 5.0 – 4 16 Industrial

SAF-XC866*-2RRA 5.0 – 4 8 Automotive

SAF-XC866*-2RRI 5.0 – 4 8 Industrial

SAK-XC866*-4RRA 3V 3.3 – 4 16 Automotive

SAK-XC866*-4RRI 3V 3.3 – 4 16 Industrial

SAK-XC866*-2RRA 3V 3.3 – 4 8 Automotive

SAK-XC866*-2RRI 3V 3.3 – 4 8 Industrial

SAF-XC866*-4RRA 3V 3.3 – 4 16 Automotive

SAF-XC866*-4RRI 3V 3.3 – 4 16 Industrial

SAF-XC866*-2RRA 3V 3.3 – 4 8 Automotive

SAF-XC866*-2RRI 3V 3.3 – 4 8 Industrial

1) Industrial is not for Automotive usage

2) The flash memory (P-Flash and D-Flash) can be used for code or data.

Table 2 Device Summary

,/ Infineon

XC866

Summary of Features

Data Sheet 5 V1.2, 2007-10

Ordering Information

The ordering code for Infineon Technologies microcontrollers provides an exact

reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery

For the available ordering codes for the XC866, please refer to your responsible sales

representative or your local distributor.

As this document refers to all the derivatives, some descriptions may not apply to a

specific product. For simplicity all versions are referred to by the term XC866 throughout

this document.

@neon

XC866

General Device Information

Data Sheet 6 V1.2, 2007-10

2 General Device Information

2.1 Block Diagram

Figure 2 XC866 Block Diagram

ADC

Port 0Port 1Port 2Port 3

CCU6

Timer 2

SSC

WDT

OCDS

8-Kbyte

Boot ROM

256-byte RAM

64-byte monitor

RAM

512-byte XRAM

4/8/16-Kbyte Flash

8/16-Kbyte ROM

XC800 Core

T0 & T1 UART

1) Includes 1-Kbyte monitor ROM

2) Includes additional 4-Kbyte Flash

P0.0 - P0.5

P1.0 - P1.1

P1.5-P1.7

P3.0 - P3.7

P2.0 - P2.7

AREF

AGND

Clock Generator

10 MHz

On-chip OSC

PLL

XTAL1

XTAL2

Internal Bus

DDP

SSP

DDC

SSC

RESET

TMS

MBC

XC866

Inflneon

XC866

General Device Information

Data Sheet 7 V1.2, 2007-10

2.2 Logic Symbol

Figure 3 XC866 Logic Symbol

XC866

DDP

SSP

DDC

SSC

AREF

AGND

XTAL1

XTAL2

TMS

RESET

MBC

Port 0 6-Bit

Port 1 5-Bit

Port 3 8-Bit

Port 2 8-Bit

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XC866

General Device Information

Data Sheet 8 V1.2, 2007-10

2.3 Pin Configuration

Figure 4 XC866 Pin Configuration, PG-TSSOP-38 Package (top view)

P0.0/TCK_0/T12HR_1/CC61_1/CLKOUT/RXDO_1

XC866

P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/CC61_3/AN0

P0.2/CTRAP_2/TDO_0/TXD_1

P0.3/SCLK_1/COUT63_1

P0.4/MTSR_1/CC62_1

P0.5/MRST_1/EXINT0_0/COUT62_1

P1.0/RXD_0/T2EX

P1.1/EXINT3/TDO_1/TXD_0

P1.5/CCPOS0_1/EXINT5/EXF2_0/RXDO_0

P1.6/CCPOS1_1/T12HR_0/EXINT6

P1.7/CCPOS2_1/T13HR_0

P2.4/AN4

P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/CC62_3/AN1

P2.2/CCPOS2_0/CTRAP_1/CC60_3/AN2

P2.3/AN3

P2.7/AN7

P2.5/AN5

P2.6/AN6

P3.0/CCPOS1_2/CC60_0

P3.1/CCPOS0_2/CC61_2/COUT60_0

P3.2/CCPOS2_2/CC61_0

P3.3/COUT61_0

P3.4/CC62_0

P3.5/COUT62_0

P3.6/CTRAP_0

P3.7/EXINT4/COUT63_0

DDP

SSP

DDC

SSC

AREF

AGND

XTAL1

XTAL2

TMS

RESET

MBC

P0.1/TDI_0/T13HR_1/RXD_1/EXF2_1/COUT61_1

n/ Infineon

XC866

General Device Information

Data Sheet 9 V1.2, 2007-10

2.4 Pin Definitions and Functions

Table 3 Pin Definitions and Functions

Symbol Pin

Number

Type Reset

State

Function

P0 I/O Port 0

Port 0 is a 6-bit bidirectional general purpose I/O

port. It can be used as alternate functions for the

JTAG, CCU6, UART, and the SSC.

P0.0 12 Hi-Z TCK_0 JTAG Clock Input

T12HR_1 CCU6 Timer 12 Hardware Run

Input

CC61_1 Input/Output of Capture/Compare

channel 1

CLKOUT Clock Output

RXDO_1 UART Transmit Data Output

P0.1 14 Hi-Z TDI_0 JTAG Serial Data Input

T13HR_1 CCU6 Timer 13 Hardware Run

Input

RXD_1 UART Receive Data Input

COUT61_1 Output of Capture/Compare

channel 1

EXF2_1 Timer 2 External Flag Output

P0.2 13 PU CTRAP_2 CCU6 Trap Input

TDO_0 JTAG Serial Data Output

TXD_1 UART Transmit Data Output/

Clock Output

P0.3 2 Hi-Z SCK_1 SSC Clock Input/Output

COUT63_1 Output of Capture/Compare

channel 3

P0.4 3 Hi-Z MTSR_1 SSC Master Transmit Output/

Slave Receive Input

CC62_1 Input/Output of Capture/Compare

channel 2

P0.5 4 Hi-Z MRST_1 SSC Master Receive Input/

Slave Transmit Output

EXINT0_0 External Interrupt Input 0

COUT62_1 Output of Capture/Compare

channel 2

n/ Infineon

XC866

General Device Information

Data Sheet 10 V1.2, 2007-10

P1 I/O Port 1

Port 1 is a 5-bit bidirectional general purpose I/O

port. It can be used as alternate functions for the

JTAG, CCU6, UART, and the SSC.

P1.0 27 PU RXD_0 UART Receive Data Input

T2EX Timer 2 External Trigger Input

P1.1 28 PU EXINT3 External Interrupt Input 3

TDO_1 JTAG Serial Data Output

TXD_0 UART Transmit Data Output/

Clock Output

P1.5 29 PU CCPOS0_1 CCU6 Hall Input 0

EXINT5 External Interrupt Input 5

EXF2_0 TImer 2 External Flag Output

RXDO_0 UART Transmit Data Output

P1.6 9 PU CCPOS1_1 CCU6 Hall Input 1

T12HR_0 CCU6 Timer 12 Hardware Run

Input

EXINT6 External Interrupt Input 6

P1.7 10 PU CCPOS2_1 CCU6 Hall Input 2

T13HR_0 CCU6 Timer 13 Hardware Run

Input

P1.5 and P1.6 can be used as a software chip

select output for the SSC.

Table 3 Pin Definitions and Functions (cont’d)

Symbol Pin

Number

Type Reset

State

Function

n/ Infineon

XC866

General Device Information

Data Sheet 11 V1.2, 2007-10

P2 IPort 2

Port 2 is an 8-bit general purpose input-only port. It

can be used as alternate functions for the digital

inputs of the JTAG and CCU6. It is also used as the

analog inputs for the ADC.

P2.0 15 Hi-Z CCPOS0_0 CCU6 Hall Input 0

EXINT1 External Interrupt Input 1

T12HR_2 CCU6 Timer 12 Hardware Run

Input

TCK_1 JTAG Clock Input

CC61_3 Input of Capture/Compare channel 1

AN0 Analog Input 0

P2.1 16 Hi-Z CCPOS1_0 CCU6 Hall Input 1

EXINT2 External Interrupt Input 2

T13HR_2 CCU6 Timer 13 Hardware Run

Input

TDI_1 JTAG Serial Data Input

CC62_3 Input of Capture/Compare channel 2

AN1 Analog Input 1

P2.2 17 Hi-Z CCPOS2_0 CCU6 Hall Input 2

CTRAP_1 CCU6 Trap Input

CC60_3 Input of Capture/Compare channel 0

AN2 Analog Input 2

P2.3 20 Hi-Z AN3 Analog Input 3

P2.4 21 Hi-Z AN4 Analog Input 4

P2.5 22 Hi-Z AN5 Analog Input 5

P2.6 23 Hi-Z AN6 Analog Input 6

P2.7 26 Hi-Z AN7 Analog Input 7

Table 3 Pin Definitions and Functions (cont’d)

Symbol Pin

Number

Type Reset

State

Function

n/ Infineon

XC866

General Device Information

Data Sheet 12 V1.2, 2007-10

P3 IPort 3

Port 3 is a bidirectional general purpose I/O port. It

can be used as alternate functions for the CCU6.

P3.0 32 Hi-Z CCPOS1_2 CCU6 Hall Input 1

CC60_0 Input/Output of Capture/Compare

channel 0

P3.1 33 Hi-Z CCPOS0_2 CCU6 Hall Input 0

CC61_2 Input/Output of Capture/Compare

channel 1

COUT60_0 Output of Capture/Compare

channel 0

P3.2 34 Hi-Z CCPOS2_2 CCU6 Hall Input 2

CC61_0 Input/Output of Capture/Compare

channel 1

P3.3 35 Hi-Z COUT61_0 Output of Capture/Compare

channel 1

P3.4 36 Hi-Z CC62_0 Input/Output of Capture/Compare

channel 2

P3.5 37 Hi-Z COUT62_0 Output of Capture/Compare

channel 2

P3.6 30 PD CTRAP_0 CCU6 Trap Input

P3.7 31 Hi-Z EXINT4 External Interrupt Input 4

COUT63_0 Output of Capture/Compare

channel 3

Table 3 Pin Definitions and Functions (cont’d)

Symbol Pin

Number

Type Reset

State

Function

Inflneon 1)

XC866

General Device Information

Data Sheet 13 V1.2, 2007-10

VDDP 18 – – I/O Port Supply (3.3 V/5.0 V)

Also used by EVR and analog modules.

VSSP 19 – – I/O Port Ground

VDDC 8––Core Supply Monitor (2.5 V)

VSSC 7––Core Supply Ground

VAREF 25 – – ADC Reference Voltage

VAGND 24 – – ADC Reference Ground

XTAL1 6IHi-ZExternal Oscillator Input

(NC if not needed)

XTAL2 5OHi-ZExternal Oscillator Output

(NC if not needed)

TMS 11 I PD Test Mode Select

RESET 38 I PU Reset Input

MBC1) 1IPUMonitor & BootStrap Loader Control

1) An external pull-up device in the range of 4.7 kΩ to 100 kΩ is required to enter user mode. Alternatively MBC

can be tied to high if alternate functions (for debugging) of the pin are not utilized.

Table 3 Pin Definitions and Functions (cont’d)

Symbol Pin

Number

Type Reset

State

Function

n/ Infineon

XC866

Functional Description

Data Sheet 14 V1.2, 2007-10

3 Functional Description

3.1 Processor Architecture

The XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is

compatible with the standard 8051 processor. While the standard 8051 processor is

designed around a 12-clock machine cycle, the XC866 CPU uses a 2-clock machine

cycle. This allows fast access to ROM or RAM memories without wait state. Access to

the Flash memory, however, requires an additional wait state (one machine cycle). The

instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.

The XC866 CPU provides a range of debugging features, including basic stop/start,

single-step execution, breakpoint support and read/write access to the data memory,

program memory and SFRs.

Figure 5 shows the CPU functional blocks.

Figure 5 CPU Block Diagram

ALU

UART

Core SFRs

16-bit Registers &

Memory Interface

Opcode Decoder

State Machine &

Power Saving

Interrupt

Controller

Multiplier / Divider

Opcode &

Immediate

Registers

Timer 0 / Timer 1

Internal Data

Memory

External SFRs

External Data

Memory

Program Memory

CCLK

Memory Wait

Reset

Legacy External Interrupts (IEN0, IEN1)

External Interrupts

Non-Maskable Interrupt

n/ Infineon

XC866

Functional Description

Data Sheet 15 V1.2, 2007-10

3.2 Memory Organization

The XC866 CPU operates in the following five address spaces:

• 8 Kbytes of Boot ROM program memory

• 256 bytes of internal RAM data memory

• 512 bytes of XRAM memory

(XRAM can be read/written as program memory or external data memory)

• a 128-byte Special Function Register area

• 4/8/16 Kbytes of Flash program memory (Flash devices); or

8/16 Kbytes of ROM program memory, with additional 4 Kbytes of Flash

(ROM devices)

Figure 6 illustrates the memory address spaces of the XC866-4FR device.

Figure 6 Memory Map of XC866 Flash Devices

0000

1000

2000

3000

F000

C000

E000

F200

FFFF

A000

B000

P-Flash Bank 1

4 Kbytes

P-Flash Bank 2

4 Kbytes

Boot ROM

8 Kbytes

XRAM

512 bytes

F000

F200

0000

FFFF

Special Function

Registers

Indirect

Address

Direct

Address

Program Space External Data Space Internal Data Space

Internal RAM

XRAM

512 bytes

Internal RAM

P-Flash Bank 0

4 Kbytes

D-Flash Bank

4 Kbytes

1) For XC866-1FR device, physically one 4KByte D-Flash bank is mapped to both address range 0000H - 0FFFH and A000H - AFFFH,

and the shaded banks are not available.

2) For XC866-2FR device, the shaded banks are not available.

n/ Infineon

XC866

Functional Description

Data Sheet 16 V1.2, 2007-10

Figure 7 illustrates the memory address spaces of the XC866-4RR device.

Figure 7 Memory Map of XC866 ROM Devices

0000

3000

F000

C000

E000

F200

A000

Boot ROM

8 KBytes

XRAM

512 Bytes

F000

F200

0000

FFFF

Special Function

Registers

Indirect

Address

Direct

Address

Code Space External Data Space Internal Data Space

Internal RAM

Memory Map User Mode

XRAM

512 Bytes

Internal RAM

User ROM

8 KBytes

1) For XC866-2RR device, the shaded area is not available and Flash is 4 Kbytes.

2) For XC866-4RR device: ROM = (12+X) KBytes, Flash = (4-X) Kbytes.

B000

Total 4 KBytes

User ROM (X bytes)

Flash (4K-X bytes)

2000

User ROM

4 KBytes

Inflneon

XC866

Functional Description

Data Sheet 17 V1.2, 2007-10

3.2.1 Memory Protection Strategy

The XC866 memory protection strategy includes:

• Read-out protection: The Flash Memory can be enabled for read-out protection and

ROM memory is always protected.

• Program and erase protection: The Flash memory in all devices can be enabled for

program and erase protection.

Flash memory protection is available in two modes:

• Mode 0: Only the P-Flash is protected; the D-Flash is unprotected

• Mode 1: Both the P-Flash and D-Flash are protected

The selection of each protection mode and the restrictions imposed are summarized in

Table 4.

BSL mode 6, which is used for enabling Flash protection, can also be used for disabling

Flash protection. Here, the programmed password must be provided by the user. A

password match triggers an automatic erase of the read-protected Flash contents, see

Table 5 and Table 6, and the programmed password is erased. The Flash protection is

then disabled upon the next reset.

For XC866-2FR and XC866-4FR devices:

The selection of protection type is summarized in Table 5.

Table 4 Flash Protection Modes

Mode 01

Activation Program a valid password via BSL mode 6

Selection MSB of password = 0 MSB of password = 1

P-Flash contents

can be read by

Read instructions in the

P-Flash

Read instructions in the

P-Flash or D-Flash

P-Flash program

and erase

Not possible Not possible

D-Flash contents

can be read by

Read instructions in any program

memory

Read instructions in the

P-Flash or D-Flash

D-Flash program Possible Not possible

D-Flash erase Possible, on the condition that bit

DFLASHEN in register MISC_CON

is set to 1 prior to each erase

operation

Not possible

n/ Infineon

XC866

Functional Description

Data Sheet 18 V1.2, 2007-10

For XC866-1FR device and ROM devices:

The selection of protection type is summarized in Table 6.

Although no protection scheme can be considered infallible, the XC866 memory

protection strategy provides a very high level of protection for a general purpose

microcontroller.

Table 5 Flash Protection Type for XC866-2FR and XC866-4FR devices

PASSWORD Type of Protection Flash Banks to Erase when

Unprotected

1XXXXXXXBFlash Protection Mode 1 All Banks

0XXXXXXXBFlash Protection Mode 0 P-Flash Bank

Table 6 Flash Protection Type for XC866-1FR device and ROM devices

PASSWORD Type of Protection

(Applicable to the

whole Flash)

Sectors to Erase

when Unprotected

Comments

1XXXXXXXBRead/Program/Erase All Sectors Compatible to

Protection mode 1

00001XXXBErase Sector 0

00010XXXBErase Sector 0 and 1

00011XXXBErase Sector 0 to 2

00100XXXBErase Sector 0 to 3

00101XXXBErase Sector 0 to 4

00110XXXBErase Sector 0 to 5

00111XXXBErase Sector 0 to 6

01000XXXBErase Sector 0 to 7

01001XXXBErase Sector 0 to 8

01010XXXBErase All Sectors

Others Erase None

n/ Infineon

XC866

Functional Description

Data Sheet 19 V1.2, 2007-10

3.2.2 Special Function Register

The Special Function Registers (SFRs) occupy direct internal data memory space in the

range 80H to FFH. All registers, except the program counter, reside in the SFR area. The

SFRs include pointers and registers that provide an interface between the CPU and the

on-chip peripherals. As the 128-SFR range is less than the total number of registers

required, address extension mechanisms are required to increase the number of

addressable SFRs. The address extension mechanisms include:

• Mapping

• Paging

3.2.2.1 Address Extension by Mapping

Address extension is performed at the system level by mapping. The SFR area is

extended into two portions: the standard (non-mapped) SFR area and the mapped SFR

area. Each portion supports the same address range 80H to FFH, bringing the number

of addressable SFRs to 256. The extended address range is not directly controlled by

the CPU instruction itself, but is derived from bit RMAP in the system control register

SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR

SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed

by clearing bit RMAP. The SFR area can be selected as shown in Figure 8.

SYSCON0

System Control Register 0 Reset Value: 00H

765432 10

010RMAP

rrwrrw

Field Bits Type Description

RMAP 0rwSpecial Function Register Map Control

0 The access to the standard SFR area is

enabled.

1 The access to the mapped SFR area is

enabled.

12rwReserved

Returns the last value if read; should be written

with 1.

01,[7:3] r Reserved

Returns 0 if read; should be written with 0.

XC866

Functional Description

Data Sheet 20 V1.2, 2007-10

Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of

SYSCON0 should not be modified.

As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not

cleared automatically by hardware. Thus, before standard/mapped registers are

accessed, bit RMAP must be cleared/set, respectively, by software.

Figure 8 Address Extension by Mapping

Module 1 SFRs

…...

SYSCON0.RMAP

SFR Data

(to/from CPU)

Standard Area (RMAP = 0)

…...

80H

FFH

80H

FFH

Direct

Internal Data

Memory Address

Mapped Area (RMAP = 1)

Module 2 SFRs

Module n SFRs

Module (n+1) SFRs

Module (n+2) SFRs

Module m SFRs

Inflneon

XC866

Functional Description

Data Sheet 21 V1.2, 2007-10

3.2.2.2 Address Extension by Paging

Address extension is further performed at the module level by paging. With the address

extension by mapping, the XC866 has a 256-SFR address range. However, this is still

less than the total number of SFRs needed by the on-chip peripherals. To meet this

requirement, some peripherals have a built-in local address extension mechanism for

increasing the number of addressable SFRs. The extended address range is not directly

controlled by the CPU instruction itself, but is derived from bit field PAGE in the module

page register MOD_PAGE. Hence, the bit field PAGE must be programmed before

accessing the SFR of the target module. Each module may contain a different number

of pages and a different number of SFRs per page, depending on the specific

requirement. Besides setting the correct RMAP bit value to select the SFR area, the user

must also ensure that a valid PAGE is selected to target the desired SFR. A page inside

the extended address range can be selected as shown in Figure 9.

Figure 9 Address Extension by Paging

SFR0

SFR1

SFRx

…...

PAGE 0

SFR0

SFR1

SFRy

…...

PAGE 1

…...

SFR0

SFR1

SFRz

…...

PAGE q

MOD_PAGE.PAGE

SFR Address

(from CPU)

SFR Data

(to/from CPU)

Module

0/ Infineon

XC866

Functional Description

Data Sheet 22 V1.2, 2007-10

In order to access a register located in a page different from the actual one, the current

page must be left. This is done by reprogramming the bit field PAGE in the page register.

Only then can the desired access be performed.

If an interrupt routine is initiated between the page register access and the module

current page setting can be saved, the new one programmed and finally, the old page

setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and

restore action of the current page setting. By indicating which storage bit field should be

used in parallel with the new page value, a single write operation can:

• Save the contents of PAGE in STx before overwriting with the new value

(this is done in the beginning of the interrupt routine to save the current page setting

and program the new page number); or

• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to

the bit positions of PAGE

(this is done at the end of the interrupt routine to restore the previous page setting

before the interrupt occurred)

Figure 10 Storage Elements for Paging

With this mechanism, a certain number of interrupt routines (or other routines) can

perform page changes without reading and storing the previously used page information.

The use of only write operations makes the system simpler and faster. Consequently,

this mechanism significantly improves the performance of short interrupt routines.

The XC866 supports local address extension for:

• Parallel Ports

• Analog-to-Digital Converter (ADC)

• Capture/Compare Unit 6 (CCU6)

• System Control Registers

PAGE

ST0

ST1

ST2

ST3

value update

from CPU

STNR

n/ Infineon rwh

XC866

Functional Description

Data Sheet 23 V1.2, 2007-10

The page register has the following definition:

MOD_PAGE

Page Register for module MOD Reset Value: 00H

765432 10

OP STNR 0 PAGE

wwrrwh

Field Bits Type Description

PAGE [2:0] rwh Page Bits

When written, the value indicates the new page.

When read, the value indicates the currently active

page.

STNR [5:4] w Storage Number

This number indicates which storage bit field is the

target of the operation defined by bit field OP.

If OP = 10B,

the contents of PAGE are saved in STx before being

overwritten with the new value.

If OP = 11B,

the contents of PAGE are overwritten by the

contents of STx. The value written to the bit positions

of PAGE is ignored.

00 ST0 is selected.

01 ST1 is selected.

10 ST2 is selected.

11 ST3 is selected.

n/ Infineon

XC866

Functional Description

Data Sheet 24 V1.2, 2007-10

OP [7:6] w Operation

0X Manual page mode. The value of STNR is

ignored and PAGE is directly written.

10 New page programming with automatic page

saving. The value written to the bit positions of

PAGE is stored. In parallel, the previous

contents of PAGE are saved in the storage bit

field STx indicated by STNR.

11 Automatic restore page action. The value

written to the bit positions PAGE is ignored

and instead, PAGE is overwritten by the

contents of the storage bit field STx indicated

by STNR.

03r Reserved

Returns 0 if read; should be written with 0.

Field Bits Type Description

n/ Infineon

XC866

Functional Description

Data Sheet 25 V1.2, 2007-10

3.2.3 Bit Protection Scheme

The bit protection scheme prevents direct software writing of selected bits (i.e., protected

bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the

bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit

field PASS closes access to writing of all protected bits. In both cases, the value of the

bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can

only be changed when bit field PASS is written with 11000B, for example, writing D0H to

PASSWD register disables the bit protection scheme.

The access is opened for maximum 32 CCLKs if the “close access” password is not

written. If “open access” password is written again before the end of 32 CCLK cycles,

there will be a recount of 32 CCLK cycles. The protected bits include NDIV, WDTEN, PD,

and SD.

PASSWD

Password Register Reset Value: 07H

76543210

PASS PROTECT

_S MODE

wrhrw

Field Bits Type Description

MODE [1:0] rw Bit Protection Scheme Control bits

00 Scheme Disabled

11 Scheme Enabled (default)

Others: Scheme Enabled

These two bits cannot be written directly. To change

the value between 11B and 00B, the bit field PASS

must be written with 11000B; only then, will the

MODE[1:0] be registered.

PROTECT_S 2rhBit Protection Signal Status bit

This bit shows the status of the protection.

0 Software is able to write to all protected bits.

1 Software is unable to write to any protected

bits.

PASS [7:3] w Password bits

The Bit Protection Scheme only recognizes three

patterns.

11000BEnables writing of the bit field MODE.

10011BOpens access to writing of all protected bits.

10101BCloses access to writing of all protected bits.

Inflneon Addr Register Name

XC866

Functional Description

Data Sheet 26 V1.2, 2007-10

3.2.4 XC866 Register Overview

The SFRs of the XC866 are organized into groups according to their functional units. The

contents (bits) of the SFRs are summarized in Table 7 to Table 15, with the addresses

of the bitaddressable SFRs appearing in bold typeface.

The CPU SFRs can be accessed in both the standard and mapped memory areas

(RMAP = 0 or 1).

Table 7 CPU Register Overview

AddrRegister Name Bit 76543210

RMAP = 0 or 1

81HSP Reset: 07H

Stack Pointer Register

Bit Field SP

Type rw

82HDPL Reset: 00H

Data Pointer Register Low

Bit Field DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0

Type rw rw rw rw rw rw rw rw

83HDPH Reset: 00H

Data Pointer Register High

Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0

Type rw rw rw rw rw rw rw rw

87HPCON Reset: 00H

Power Control Register

Bit Field SMOD 0GF1 GF0 0IDLE

Type rw r rw rw r rw

88HTCON Reset: 00H

Timer Control Register

Bit Field TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Type rwh rw rwh rw rwh rw rwh rw

89HTMOD Reset: 00H

Timer Mode Register

Bit Field GATE1 0T1M GATE0 0T0M

Type rw r rw rw r rw

8AHTL0 Reset: 00H

Timer 0 Register Low

Bit Field VAL

Type rwh

8BHTL1 Reset: 00H

Timer 1 Register Low

Bit Field VAL

Type rwh

8CHTH0 Reset: 00H

Timer 0 Register High

Bit Field VAL

Type rwh

8DHTH1 Reset: 00H

Timer 1 Register High

Bit Field VAL

Type rwh

98HSCON Reset: 00H

Serial Channel Control Register

Bit Field SM0 SM1 SM2 REN TB8 RB8 TI RI

Type rw rw rw rw rw rwh rwh rwh

99HSBUF Reset: 00H

Serial Data Buffer Register

Bit Field VAL

Type rwh

A2HEO Reset: 00H

Extended Operation Register

Bit Field 0TRAP_

0DPSEL

Type r rw r rw

A8HIEN0 Reset: 00H

Interrupt Enable Register 0

Bit Field EA 0ET2 ES ET1 EX1 ET0 EX0

Type rw r rwrwrwrwrwrw

B8HIP Reset: 00H

Interrupt Priority Register

Bit Field 0PT2 PS PT1 PX1 PT0 PX0

Type r rwrwrwrwrwrw

B9HIPH Reset: 00H

Interrupt Priority Register High

Bit Field 0PT2H PSH PT1H PX1H PT0H PX0H

Type r rwrwrwrwrwrw

D0HPSW Reset: 00H

Program Status Word Register

Bit Field CY AC F0 RS1 RS0 OV F1 P

Type rw rwh rwh rw rw rwh rwh rh

E0HACC Reset: 00H

Accumulator Register

Bit Field ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0

Type rw rw rw rw rw rw rw rw

E8HIEN1 Reset: 00H

Interrupt Enable Register 1

Bit Field ECCIP

ECCIP

EXM EX2 ESSC EADC

Type rw rw rw rw rw rw rw rw

@neon Addr Register Name Addr Register Name

XC866

Functional Description

Data Sheet 27 V1.2, 2007-10

The system control SFRs can be accessed in the standard memory area (RMAP = 0).

F0HB Reset: 00H

B Register

Bit Field B7 B6 B5 B4 B3 B2 B1 B0

Type rw rw rw rw rw rw rw rw

F8HIP1 Reset: 00H

Interrupt Priority Register 1

Bit Field PCCIP

PCCIP

PXM PX2 PSSC PADC

Type rw rw rw rw rw rw rw rw

F9HIPH1 Reset: 00H

Interrupt Priority Register 1 High

Bit Field PCCIP

PCCIP

PXMH PX2H PSSCH PADC

Type rw rw rw rw rw rw rw rw

Table 8 System Control Register Overview

AddrRegister Name Bit 76543210

RMAP = 0 or 1

8FHSYSCON0 Reset: 00H

System Control Register 0

Bit Field 0RMAP

Type r rw

RMAP = 0

BFHSCU_PAGE Reset: 00H

Page Register for System Control

Bit Field OP STNR 0PAGE

Type w w rrwh

RMAP = 0, Page 0

B3HMODPISEL Reset: 00H

Peripheral Input Select Register

Bit Field 0JTAG

TDIS

JTAG

TCKS

0EXINT

0IS

URRIS

Type r rw rw rrw rw

B4HIRCON0 Reset: 00H

Interrupt Request Register 0

Bit Field 0EXINT

EXINT

Type r rwh rwh rwh rwh rwh rwh rwh

B5HIRCON1 Reset: 00H

Interrupt Request Register 1

Bit Field 0ADCS

RC1

ADCS

RC0

RIR TIR EIR

Type r rwh rwh rwh rwh rwh

B7HEXICON0 Reset: 00H

External Interrupt Control Register 0

Bit Field EXINT3 EXINT2 EXINT1 EXINT0

Type rw rw rw rw

BAHEXICON1 Reset: 00H

External Interrupt Control Register 1

Bit Field 0EXINT6 EXINT5 EXINT4

Type r rw rw rw

BBHNMICON Reset: 00H

NMI Control Register

Bit Field 0NMI

ECC

NMI

VDDP

NMI

VDD

NMI

OCDS

NMI

FLASH

NMI

PLL

NMI

WDT

Type r rw rw rw rw rw rw rw

BCHNMISR Reset: 00H

NMI Status Register

Bit Field 0FNMI

ECC

FNMI

VDDP

FNMI

VDD

FNMI

OCDS

FNMI

FLASH

FNMI

PLL

FNMI

WDT

Type r rwh rwh rwh rwh rwh rwh rwh

BDHBCON Reset: 00H

Baud Rate Control Register

Bit Field BGSEL 0BREN BRPRE R

Type rw r rw rw rw

BEHBG Reset: 00H

Baud Rate Timer/Reload Register

Bit Field BR_VALUE

Type rw

E9HFDCON Reset: 00H

Fractional Divider Control Register

Bit Field BGS SYNEN ERRSY

EOFSY

BRK NDOV FDM FDEN

Type rw rw rwh rwh rwh rwh rw rw

EAHFDSTEP Reset: 00H

Fractional Divider Reload Register

Bit Field STEP

Type rw

EBHFDRES Reset: 00H

Fractional Divider Result Register

Bit Field RESULT

Type rh

RMAP = 0, Page 1

Table 7 CPU Register Overview (cont’d)

AddrRegister Name Bit 76543210

@neon Addr Register Name Addr Register Name

XC866

Functional Description

Data Sheet 28 V1.2, 2007-10

The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).

B3HID Reset: 01H

Identity Register

Bit Field PRODID VERID

Type r r

B4HPMCON0 Reset: 00H

Power Mode Control Register 0

Bit Field 0WDT

RST

WKRS WK

SEL

SD PD WS

Type r rwh rwh rw rw rwh rw

B5HPMCON1 Reset: 00H

Power Mode Control Register 1

Bit Field 0T2_DIS CCU

_DIS

SSC

_DIS

ADC

_DIS

Type r rw rw rw rw

B6HOSC_CON Reset: 08H

OSC Control Register

Bit Field 0OSC

XPD OSC

ORD

RES

OSCR

Type r rw rw rw rwh rh

B7HPLL_CON Reset: 20H

PLL Control Register

Bit Field NDIV VCO

BYP

OSC

DISC

RESLD LOCK

Type rw rw rw rwh rh

BAHCMCON Reset: 00H

Clock Control Register

Bit Field VCO

SEL

0CLKREL

Type rw r rw

BBHPASSWD Reset: 07H

Password Register

Bit Field PASS PROTE

CT_S

MODE

Type w rh rw

BCHFEAL Reset: 00H

Flash Error Address Register Low

Bit Field ECCERRADDR[7:0]

Type rh

BDHFEAH Reset: 00H

Flash Error Address Register High

Bit Field ECCERRADDR[15:8]

Type rh

BEHCOCON Reset: 00H

Clock Output Control Register

Bit Field 0TLEN COUT

COREL

Type r rw rw rw

E9HMISC_CON Reset: 00H

Miscellaneous Control Register

Bit Field 0DFLAS

HEN

Type r rwh

RMAP = 0, Page 3

B3HXADDRH Reset: F0H

On-Chip XRAM Address Higher Order

Bit Field ADDRH

Type rw

Table 9 WDT Register Overview

AddrRegister Name Bit 76543210

RMAP = 1

BBHWDTCON Reset: 00H

Watchdog Timer Control Register

Bit Field 0WINB

WDT

0WDT

WDT

Type r rw rh rrw rwh rw

BCHWDTREL Reset: 00H

Watchdog Timer Reload Register

Bit Field WDTREL

Type rw

BDHWDTWINB Reset: 00H

Watchdog Window-Boundary Count

Bit Field WDTWINB

Type rw

BEHWDTL Reset: 00H

Watchdog Timer Register Low

Bit Field WDT[7:0]

Type rh

BFHWDTH Reset: 00H

Watchdog Timer Register High

Bit Field WDT[15:8]

Type rh

Table 8 System Control Register Overview (cont’d)

AddrRegister Name Bit 76543210

@neon Addr Register Name

XC866

Functional Description

Data Sheet 29 V1.2, 2007-10

The Port SFRs can be accessed in the standard memory area (RMAP = 0).

Table 10 Port Register Overview

AddrRegister Name Bit 76543210

RMAP = 0

B2HPORT_PAGE Reset: 00H

Page Register for PORT

Bit Field OP STNR 0PAGE

Type w w rrwh

RMAP = 0, Page 0

80HP0_DATA Reset: 00H

P0 Data Register

Bit Field 0P5 P4 P3 P2 P1 P0

Type r rwh rwh rwh rwh rwh rwh

86HP0_DIR Reset: 00H

P0 Direction Register

Bit Field 0P5 P4 P3 P2 P1 P0

Type r rw rw rw rw rw rw

90HP1_DATA Reset: 00H

P1 Data Register

Bit Field P7 P6 P5 0P1 P0

Type rwh rwh rwh r rwh rwh

91HP1_DIR Reset: 00H

P1 Direction Register

Bit Field P7 P6 P5 0P1 P0

Type rw rw rw r rw rw

A0HP2_DATA Reset: 00H

P2 Data Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rwhrwhrwhrwhrwh rwh rwh rwh

A1HP2_DIR Reset: 00H

P2 Direction Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rw rw rw rw rw rw rw rw

B0HP3_DATA Reset: 00H

P3 Data Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rwhrwhrwhrwhrwh rwh rwh rwh

B1HP3_DIR Reset: 00H

P3 Direction Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rw rw rw rw rw rw rw rw

RMAP = 0, Page 1

80HP0_PUDSEL Reset: FFH

P0 Pull-Up/Pull-Down Select Register

Bit Field 0P5 P4 P3 P2 P1 P0

Type r rw rw rw rw rw rw

86HP0_PUDEN Reset: C4H

P0 Pull-Up/Pull-Down Enable Register

Bit Field 0P5 P4 P3 P2 P1 P0

Type r rw rw rw rw rw rw

90HP1_PUDSEL Reset: FFH

P1 Pull-Up/Pull-Down Select Register

Bit Field P7 P6 P5 0P1 P0

Type rw rw rw r rw rw

91HP1_PUDEN Reset: FFH

P1 Pull-Up/Pull-Down Enable Register

Bit Field P7 P6 P5 0P1 P0

Type rw rw rw r rw rw

A0HP2_PUDSEL Reset: FFH

P2 Pull-Up/Pull-Down Select Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rw rw rw rw rw rw rw rw

A1HP2_PUDEN Reset: 00H

P2 Pull-Up/Pull-Down Enable Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rw rw rw rw rw rw rw rw

B0HP3_PUDSEL Reset: BFH

P3 Pull-Up/Pull-Down Select Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rw rw rw rw rw rw rw rw

B1HP3_PUDEN Reset: 40H

P3 Pull-Up/Pull-Down Enable Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rw rw rw rw rw rw rw rw

RMAP = 0, Page 2

80HP0_ALTSEL0 Reset: 00H

P0 Alternate Select 0 Register

Bit Field 0P5 P4 P3 P2 P1 P0

Type r rw rw rw rw rw rw

86HP0_ALTSEL1 Reset: 00H

P0 Alternate Select 1 Register

Bit Field 0P5 P4 P3 P2 P1 P0

Type r rw rw rw rw rw rw

90HP1_ALTSEL0 Reset: 00H

P1 Alternate Select 0 Register

Bit Field P7 P6 P5 0P1 P0

Type rw rw rw r rw rw

91HP1_ALTSEL1 Reset: 00H

P1 Alternate Select 1 Register

Bit Field P7 P6 P5 0P1 P0

Type rw rw rw r rw rw

B0HP3_ALTSEL0 Reset: 00H

P3 Alternate Select 0 Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rw rw rw rw rw rw rw rw

@neon Addr Register Name Addr Register Name

XC866

Functional Description

Data Sheet 30 V1.2, 2007-10

The ADC SFRs can be accessed in the standard memory area (RMAP = 0).

B1HP3_ALTSEL1 Reset: 00H

P3 Alternate Select 1 Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rw rw rw rw rw rw rw rw

RMAP = 0, Page 3

80HP0_OD Reset: 00H

P0 Open Drain Control Register

Bit Field 0P5 P4 P3 P2 P1 P0

Type r rw rw rw rw rw rw

90HP1_OD Reset: 00H

P1 Open Drain Control Register

Bit Field P7 P6 P5 0P1 P0

Type rw rw rw r rw rw

B0HP3_OD Reset: 00H

P3 Open Drain Control Register

Bit Field P7 P6 P5 P4 P3 P2 P1 P0

Type rw rw rw rw rw rw rw rw

Table 11 ADC Register Overview

AddrRegister Name Bit 76543210

RMAP = 0

D1HADC_PAGE Reset: 00H

Page Register for ADC

Bit Field OP STNR 0PAGE

Type w w rrwh

RMAP = 0, Page 0

CAHADC_GLOBCTR Reset: 30H

Global Control Register

Bit Field ANON DW CTC 0

Type rw rw rw r

CBHADC_GLOBSTR Reset: 00H

Global Status Register

Bit Field 0CHNR 0SAM

PLE

BUSY

Type r rh rrh rh

CCHADC_PRAR Reset: 00H

Priority and Arbitration Register

Bit Field ASEN1 ASEN0 0ARBM CSM1 PRIO1 CSM0 PRIO0

Type rw rw r rw rw rw rw rw

CDHADC_LCBR Reset: B7H

Limit Check Boundary Register

Bit Field BOUND1 BOUND0

Type rw rw

CEHADC_INPCR0 Reset: 00H

Input Class Register 0

Bit Field STC

Type rw

CFHADC_ETRCR Reset: 00H

External Trigger Control Register

Bit Field SYNEN

SYNEN

ETRSEL1 ETRSEL0

Type rw rw rw rw

RMAP = 0, Page 1

CAHADC_CHCTR0 Reset: 00H

Channel Control Register 0

Bit Field 0LCC 0RESRSEL

Type r rw rrw

CBHADC_CHCTR1 Reset: 00H

Channel Control Register 1

Bit Field 0LCC 0RESRSEL

Type r rw rrw

CCHADC_CHCTR2 Reset: 00H

Channel Control Register 2

Bit Field 0LCC 0RESRSEL

Type r rw rrw

CDHADC_CHCTR3 Reset: 00H

Channel Control Register 3

Bit Field 0LCC 0RESRSEL

Type r rw rrw

CEHADC_CHCTR4 Reset: 00H

Channel Control Register 4

Bit Field 0LCC 0RESRSEL

Type r rw rrw

CFHADC_CHCTR5 Reset: 00H

Channel Control Register 5

Bit Field 0LCC 0RESRSEL

Type r rw rrw

D2HADC_CHCTR6 Reset: 00H

Channel Control Register 6

Bit Field 0LCC 0RESRSEL

Type r rw rrw

D3HADC_CHCTR7 Reset: 00H

Channel Control Register 7

Bit Field 0LCC 0RESRSEL

Type r rw rrw

RMAP = 0, Page 2

Table 10 Port Register Overview (cont’d)

AddrRegister Name Bit 76543210

@neon Addr Register Name

XC866

Functional Description

Data Sheet 31 V1.2, 2007-10

CAHADC_RESR0L Reset: 00H

Result Register 0 Low

Bit Field RESULT[1:0] 0VF DRC CHNR

Type rh r rh rh rh

CBHADC_RESR0H Reset: 00H

Result Register 0 High

Bit Field RESULT[9:2]

Type rh

CCHADC_RESR1L Reset: 00H

Result Register 1 Low

Bit Field RESULT[1:0] 0VF DRC CHNR

Type rh r rh rh rh

CDHADC_RESR1H Reset: 00H

Result Register 1 High

Bit Field RESULT[9:2]

Type rh

CEHADC_RESR2L Reset: 00H

Result Register 2 Low

Bit Field RESULT[1:0] 0VF DRC CHNR

Type rh r rh rh rh

CFHADC_RESR2H Reset: 00H

Result Register 2 High

Bit Field RESULT[9:2]

Type rh

D2HADC_RESR3L Reset: 00H

Result Register 3 Low

Bit Field RESULT[1:0] 0VF DRC CHNR

Type rh r rh rh rh

D3HADC_RESR3H Reset: 00H

Result Register 3 High

Bit Field RESULT[9:2]

Type rh

RMAP = 0, Page 3

CAHADC_RESRA0L Reset: 00H

Result Register 0, View A Low

Bit Field RESULT[2:0] VF DRC CHNR

Type rh rh rh rh

CBHADC_RESRA0H Reset: 00H

Result Register 0, View A High

Bit Field RESULT[10:3]

Type rh

CCHADC_RESRA1L Reset: 00H

Result Register 1, View A Low

Bit Field RESULT[2:0] VF DRC CHNR

Type rh rh rh rh

CDHADC_RESRA1H Reset: 00H

Result Register 1, View A High

Bit Field RESULT[10:3]

Type rh

CEHADC_RESRA2L Reset: 00H

Result Register 2, View A Low

Bit Field RESULT[2:0] VF DRC CHNR

Type rh rh rh rh

CFHADC_RESRA2H Reset: 00H

Result Register 2, View A High

Bit Field RESULT[10:3]

Type rh

D2HADC_RESRA3L Reset: 00H

Result Register 3, View A Low

Bit Field RESULT[2:0] VF DRC CHNR

Type rh rh rh rh

D3HADC_RESRA3H Reset: 00H

Result Register 3, View A High

Bit Field RESULT[10:3]

Type rh

RMAP = 0, Page 4

CAHADC_RCR0 Reset: 00H

Result Control Register 0

Bit Field VFCTR WFR 0IEN 0DRCT

Type rw rw r rw rrw

CBHADC_RCR1 Reset: 00H

Result Control Register 1

Bit Field VFCTR WFR 0IEN 0DRCT

Type rw rw r rw rrw

CCHADC_RCR2 Reset: 00H

Result Control Register 2

Bit Field VFCTR WFR 0IEN 0DRCT

Type rw rw r rw rrw

CDHADC_RCR3 Reset: 00H

Result Control Register 3

Bit Field VFCTR WFR 0IEN 0DRCT

Type rw rw r rw rrw

CEHADC_VFCR Reset: 00H

Valid Flag Clear Register

Bit Field 0VFC3 VFC2 VFC1 VFC0

Type r wwww

RMAP = 0, Page 5

Table 11 ADC Register Overview (cont’d)

AddrRegister Name Bit 76543210

@neon Addr Register Name Addr Register Name Bil

XC866

Functional Description

Data Sheet 32 V1.2, 2007-10

The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).

CAHADC_CHINFR Reset: 00H

Channel Interrupt Flag Register

Bit Field CHINF

CHINF

Type rh rh rh rh rh rh rh rh

CBHADC_CHINCR Reset: 00H

Channel Interrupt Clear Register

Bit Field CHINC

CHINC

Type wwwwwwww

CCHADC_CHINSR Reset: 00H

Channel Interrupt Set Register

Bit Field CHINS

CHINS

Type wwwwwwww

CDHADC_CHINPR Reset: 00H

Channel Interrupt Node Pointer

Bit Field CHINP

CHINP

Type rw rw rw rw rw rw rw rw

CEHADC_EVINFR Reset: 00H

Event Interrupt Flag Register

Bit Field EVINF

EVINF

0EVINF

EVINF

Type rh rh rh rh rrh rh

CFHADC_EVINCR Reset: 00H

Event Interrupt Clear Flag Register

Bit Field EVINC

EVINC

0EVINC

EVINC

Type wwww r w w

D2HADC_EVINSR Reset: 00H

Event Interrupt Set Flag Register

Bit Field EVINS

EVINS

0EVINS

EVINS

Type wwww r w w

D3HADC_EVINPR Reset: 00H

Event Interrupt Node Pointer Register

Bit Field EVINP

EVINP

0EVINP

EVINP

Type rw rw rw rw rrw rw

RMAP = 0, Page 6

CAHADC_CRCR1 Reset: 00H

Conversion Request Control Register 1

Bit Field CH7 CH6 CH5 CH4 0

Type rwhrwhrwhrwh r

CBHADC_CRPR1 Reset: 00H

Conversion Request Pending

Bit Field CHP7 CHP6 CHP5 CHP4 0

Type rwhrwhrwhrwh r

CCHADC_CRMR1 Reset: 00H

Conversion Request Mode Register 1

Bit Field Rsv LDEV CLR

PND

SCAN ENSI ENTR ENGT

Type r w w rw rw rw rw

CDHADC_QMR0 Reset: 00H

Queue Mode Register 0

Bit Field CEV TREV FLUSH CLRV TRMD ENTR ENGT

Type wwwwrw rw rw

CEHADC_QSR0 Reset: 20H

Queue Status Register 0

Bit Field Rsv 0EMPTY EV 0

Type r r rh rh r

CFHADC_Q0R0 Reset: 00H

Queue 0 Register 0

Bit Field EXTR ENSI RF V 0 REQCHNR

Type rh rh rh rh rrh

D2HADC_QBUR0 Reset: 00H

Queue Backup Register 0

Bit Field EXTR ENSI RF V 0 REQCHNR

Type rh rh rh rh rrh

D2HADC_QINR0 Reset: 00H

Queue Input Register 0

Bit Field EXTR ENSI RF 0REQCHNR

Type www r w

Table 12 Timer 2 Register Overview

AddrRegister Name Bit 76543210

C0HT2_T2CON Reset: 00H

Timer 2 Control Register

Bit Field TF2 EXF2 0EXEN2 TR2 0CP/

RL2

Type rwh rwh r rw rwh rrw

Table 11 ADC Register Overview (cont’d)

AddrRegister Name Bit 76543210

Inflneon Addr Register Name

XC866

Functional Description

Data Sheet 33 V1.2, 2007-10

The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).

C1HT2_T2MOD Reset: 00H

Timer 2 Mode Register

Bit Field T2

REGS

RHEN

EDGE

SEL

PREN T2PRE DCEN

Type rw rw rw rw rw rw

C2HT2_RC2L Reset: 00H

Timer 2 Reload/Capture Register Low

Bit Field RC2[7:0]

Type rwh

C3HT2_RC2H Reset: 00H

Timer 2 Reload/Capture Register High

Bit Field RC2[15:8]

Type rwh

C4HT2_T2L Reset: 00H

Timer 2 Register Low

Bit Field THL2[7:0]

Type rwh

C5HT2_T2H Reset: 00H

Timer 2 Register High

Bit Field THL2[15:8]

Type rwh

Table 13 CCU6 Register Overview

AddrRegister Name Bit 76543210

RMAP = 0

A3HCCU6_PAGE Reset: 00H

Page Register for CCU6

Bit Field OP STNR 0PAGE

Type w w rrwh

RMAP = 0, Page 0

9AHCCU6_CC63SRL Reset: 00H

Capture/Compare Shadow Register for

Channel CC63 Low

Bit Field CC63SL

Type rw

9BHCCU6_CC63SRH Reset: 00H

Capture/Compare Shadow Register for

Channel CC63 High

Bit Field CC63SH

Type rw

9CHCCU6_TCTR4L Reset: 00H

Timer Control Register 4 Low

Bit Field T12

STD

T12

STR

0DTRES T12

RES

T12RS T12RR

Type w w r wwww

9DHCCU6_TCTR4H Reset: 00H

Timer Control Register 4 High

Bit Field T13

STD

T13

STR

0T13

RES

T13RS T13RR

Type w w r www

9EHCCU6_MCMOUTSL Reset: 00H

Multi-Channel Mode Output Shadow

Bit Field STRM

0MCMPS

Type w r rw

9FHCCU6_MCMOUTSH Reset: 00H

Multi-Channel Mode Output Shadow

Bit Field STRHP 0CURHS EXPHS

Type w r rw rw

A4HCCU6_ISRL Reset: 00H

Capture/Compare Interrupt Status

Reset Register Low

Bit Field RT12P

RT12O

RCC62

RCC61

RCC60

Type wwwwwwww

A5HCCU6_ISRH Reset: 00H

Capture/Compare Interrupt Status

Reset Register High

Bit Field RSTR RIDLE RWHE RCHE 0RTRPF RT13

RT13

Type wwww r w w w

A6HCCU6_CMPMODIFL Reset: 00H

Compare State Modification Register

Low

Bit Field 0MCC63

0MCC62

MCC61

MCC60

Type r w r www

A7HCCU6_CMPMODIFH Reset: 00H

Compare State Modification Register

High

Bit Field 0MCC63

0MCC62

MCC61

MCC60

Type r w r www

FAHCCU6_CC60SRL Reset: 00H

Capture/Compare Shadow Register for

Channel CC60 Low

Bit Field CC60SL

Type rwh

Table 12 Timer 2 Register Overview (cont’d)

@neon Addr Register Name

XC866

Functional Description

Data Sheet 34 V1.2, 2007-10

FBHCCU6_CC60SRH Reset: 00H

Capture/Compare Shadow Register for

Channel CC60 High

Bit Field CC60SH

Type rwh

FCHCCU6_CC61SRL Reset: 00H

Capture/Compare Shadow Register for

Channel CC61 Low

Bit Field CC61SL

Type rwh

FDHCCU6_CC61SRH Reset: 00H

Capture/Compare Shadow Register for

Channel CC61 High

Bit Field CC61SH

Type rwh

FEHCCU6_CC62SRL Reset: 00H

Capture/Compare Shadow Register for

Channel CC62 Low

Bit Field CC62SL

Type rwh

FFHCCU6_CC62SRH Reset: 00H

Capture/Compare Shadow Register for

Channel CC62 High

Bit Field CC62SH

Type rwh

RMAP = 0, Page 1

9AHCCU6_CC63RL Reset: 00H

Capture/Compare Register for Channel

CC63 Low

Bit Field CC63VL

Type rh

9BHCCU6_CC63RH Reset: 00H

Capture/Compare Register for Channel

CC63 High

Bit Field CC63VH

Type rh

9CHCCU6_T12PRL Reset: 00H

Timer T12 Period Register Low

Bit Field T12PVL

Type rwh

9DHCCU6_T12PRH Reset: 00H

Timer T12 Period Register High

Bit Field T12PVH

Type rwh

9EHCCU6_T13PRL Reset: 00H

Timer T13 Period Register Low

Bit Field T13PVL

Type rwh

9FHCCU6_T13PRH Reset: 00H

Timer T13 Period Register High

Bit Field T13PVH

Type rwh

A4HCCU6_T12DTCL Reset: 00H

Dead-Time Control Register for Timer

T12 Low

Bit Field DTM

Type rw

A5HCCU6_T12DTCH Reset: 00H

Dead-Time Control Register for Timer

T12 High

Bit Field 0DTR2 DTR1 DTR0 0DTE2 DTE1 DTE0

Type r rhrhrh rrw rw rw

A6HCCU6_TCTR0L Reset: 00H

Timer Control Register 0 Low

Bit Field CTM CDIR STE12 T12R T12

PRE

T12CLK

Type rw rh rh rh rw rw

A7HCCU6_TCTR0H Reset: 00H

Timer Control Register 0 High

Bit Field 0STE13 T13R T13

PRE

T13CLK

Type r rh rh rw rw

FAHCCU6_CC60RL Reset: 00H

Capture/Compare Register for Channel

CC60 Low

Bit Field CC60VL

Type rh

FBHCCU6_CC60RH Reset: 00H

Capture/Compare Register for Channel

CC60 High

Bit Field CC60VH

Type rh

FCHCCU6_CC61RL Reset: 00H

Capture/Compare Register for Channel

CC61 Low

Bit Field CC61VL

Type rh

Table 13 CCU6 Register Overview (cont’d)

AddrRegister Name Bit 76543210

@neon Addr Register Name

XC866

Functional Description

Data Sheet 35 V1.2, 2007-10

FDHCCU6_CC61RH Reset: 00H

Capture/Compare Register for Channel

CC61 High

Bit Field CC61VH

Type rh

FEHCCU6_CC62RL Reset: 00H

Capture/Compare Register for Channel

CC62 Low

Bit Field CC62VL

Type rh

FFHCCU6_CC62RH Reset: 00H

Capture/Compare Register for Channel

CC62 High

Bit Field CC62VH

Type rh

RMAP = 0, Page 2

9AHCCU6_T12MSELL Reset: 00H

T12 Capture/Compare Mode Select

Bit Field MSEL61 MSEL60

Type rw rw

9BHCCU6_T12MSELH Reset: 00H

T12 Capture/Compare Mode Select

Bit Field DBYP HSYNC MSEL62

Type rw rw rw

9CHCCU6_IENL Reset: 00H

Capture/Compare Interrupt Enable

Bit Field ENT12

ENT12

ENCC

62F

ENCC

62R

ENCC

61F

ENCC

61R

ENCC

60F

ENCC

60R

Type rw rw rw rw rw rw rw rw

9DHCCU6_IENH Reset: 00H

Capture/Compare Interrupt Enable

Bit Field ENSTR EN

IDLE

WHE

CHE

0EN

TRPF

ENT13

Type rw rw rw rw rrw rw rw

9EHCCU6_INPL Reset: 40H

Capture/Compare Interrupt Node

Pointer Register Low

Bit Field INPCHE INPCC62 INPCC61 INPCC60

Type rw rw rw rw

9FHCCU6_INPH Reset: 39H

Capture/Compare Interrupt Node

Pointer Register High

Bit Field 0INPT13 INPT12 INPERR

Type r rw rw rw

A4HCCU6_ISSL Reset: 00H

Capture/Compare Interrupt Status Set

Bit Field ST12P

ST12O

SCC62

SCC61

SCC60

Type wwwwwwww

A5HCCU6_ISSH Reset: 00H

Capture/Compare Interrupt Status Set

Bit Field SSTR SIDLE SWHE SCHE SWHC STRPF ST13

ST13

Type wwwwwwww

A6HCCU6_PSLR Reset: 00H

Passive State Level Register

Bit Field PSL63 0PSL

Type rwh r rwh

A7HCCU6_MCMCTR Reset: 00H

Multi-Channel Mode Control Register

Bit Field 0SWSYN 0SWSEL

Type r rw rrw

FAHCCU6_TCTR2L Reset: 00H

Timer Control Register 2 Low

Bit Field 0T13TED T13TEC T13

SSC

T12

SSC

Type r rw rw rw rw

FBHCCU6_TCTR2H Reset: 00H

Timer Control Register 2 High

Bit Field 0T13RSEL T12RSEL

Type r rw rw

FCHCCU6_MODCTRL Reset: 00H

Modulation Control Register Low

Bit Field MC

MEN

0T12MODEN

Type rw r rw

FDHCCU6_MODCTRH Reset: 00H

Modulation Control Register High

Bit Field ECT13

0T13MODEN

Type rw r rw

FEHCCU6_TRPCTRL Reset: 00H

Trap Control Register Low

Bit Field 0TRPM2 TRPM1 TRPM0

Type r rw rw rw

Table 13 CCU6 Register Overview (cont’d)

AddrRegister Name Bit 76543210

@neon Addr Register Name Addr Register Name

XC866

Functional Description

Data Sheet 36 V1.2, 2007-10

The SSC SFRs can be accessed in the standard memory area (RMAP = 0).

FFHCCU6_TRPCTRH Reset: 00H

Trap Control Register High

Bit Field TRPPE

TRPEN

Type rw rw rw

RMAP = 0, Page 3

9AHCCU6_MCMOUTL Reset: 00H

Multi-Channel Mode Output Register

Low

Bit Field 0 R MCMP

Type r rh rh

9BHCCU6_MCMOUTH Reset: 00H

Multi-Channel Mode Output Register

High

Bit Field 0CURH EXPH

Type r rh rh

9CHCCU6_ISL Reset: 00H

Capture/Compare Interrupt Status

Bit Field T12PM T12OM ICC62F ICC62

ICC61F ICC61

ICC60F ICC60

Type rh rh rh rh rh rh rh rh

9DHCCU6_ISH Reset: 00H

Capture/Compare Interrupt Status

Bit Field STR IDLE WHE CHE TRPS TRPF T13PM T13CM

Type rh rh rh rh rh rh rh rh

9EHCCU6_PISEL0L Reset: 00H

Port Input Select Register 0 Low

Bit Field ISTRP ISCC62 ISCC61 ISCC60

Type rw rw rw rw

9FHCCU6_PISEL0H Reset: 00H

Port Input Select Register 0 High

Bit Field IST12HR ISPOS2 ISPOS1 ISPOS0

Type rw rw rw rw

A4HCCU6_PISEL2 Reset: 00H

Port Input Select Register 2

Bit Field 0IST13HR

Type r rw

FAHCCU6_T12L Reset: 00H

Timer T12 Counter Register Low

Bit Field T12CVL

Type rwh

FBHCCU6_T12H Reset: 00H

Timer T12 Counter Register High

Bit Field T12CVH

Type rwh

FCHCCU6_T13L Reset: 00H

Timer T13 Counter Register Low

Bit Field T13CVL

Type rwh

FDHCCU6_T13H Reset: 00H

Timer T13 Counter Register High

Bit Field T13CVH

Type rwh

FEHCCU6_CMPSTATL Reset: 00H

Compare State Register Low

Bit Field 0CC63

CCPO

CC62

CC61

CC60

Type r rhrhrhrh rh rh rh

FFHCCU6_CMPSTATH Reset: 00H

Compare State Register High

Bit Field T13IM COUT

63PS

COUT

62PS

CC62

COUT

61PS

CC61

COUT

60PS

CC60

Type rwhrwhrwhrwhrwh rwh rwh rwh

Table 14 SSC Register Overview

AddrRegister Name Bit 76543210

RMAP = 0

A9HSSC_PISEL Reset: 00H

Port Input Select Register

Bit Field 0 CIS SIS MIS

Type r rw rw rw

AAHSSC_CONL Reset: 00H

Control Register Low

Programming Mode

Bit Field LB PO PH HB BM

Type rw rw rw rw rw

Operating Mode Bit Field 0BC

Type r rh

Table 13 CCU6 Register Overview (cont’d)

AddrRegister Name Bit 76543210

Inflneon Addr Register Name

XC866

Functional Description

Data Sheet 37 V1.2, 2007-10

The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).

ABHSSC_CONH Reset: 00H

Control Register High

Programming Mode

Bit Field EN MS 0AREN BEN PEN REN TEN

Type rw rw r rw rw rw rw rw

Operating Mode Bit Field EN MS 0BSY BE PE RE TE

Type rw rw r rh rwh rwh rwh rwh

ACHSSC_TBL Reset: 00H

Transmitter Buffer Register Low

Bit Field TB_VALUE

Type rw

ADHSSC_RBL Reset: 00H

Receiver Buffer Register Low

Bit Field RB_VALUE

Type rh

AEHSSC_BRL Reset: 00H

Baudrate Timer Reload Register Low

Bit Field BR_VALUE[7:0]

Type rw

AFHSSC_BRH Reset: 00H

Baudrate Timer Reload Register High

Bit Field BR_VALUE[15:8]

Type rw

Table 15 OCDS Register Overview

AddrRegister Name Bit 76543210

RMAP = 1

E9HMMCR2 Reset: 0UH

Monitor Mode Control Register 2

Bit Field EXBC_

EXBC MBCO

N_P

MBCO

MMEP

MMEP MMOD

JENA

Type w rw w rwh wrwh rh rh

F1HMMCR Reset: 00H

Monitor Mode Control Register

Bit Field MEXIT

MEXIT MSTEP

MSTEP MRAM

S_P

MRAM

TRF RRF

Type w rwh w rw wrwh rh rh

F2HMMSR Reset: 00H

Monitor Mode Status Register

Bit Field MBCA

MBCIN EXBF SWBF HWB3

HWB2

HWB1

HWB0

Type rw rh rwh rwh rwh rwh rwh rwh

F3HMMBPCR Reset: 00H

BreakPoints Control Register

Bit Field SWBC HWB3C HWB2C HWB1

HWB0C

Type rw rw rw rw rw

F4HMMICR Reset: 00H

Monitor Mode Interrupt Control Register

Bit Field DVECT DRETR 0MMUIE

MMUIE RRIE_

RRIE

Type rwh rwh r wrw wrw

F5HMMDR Reset: 00H

Monitor Mode Data Register

Receive

Bit Field MMRR

Type rh

Transmit Bit Field MMTR

Type w

F6HHWBPSR Reset: 00H

Hardware Breakpoints Select Register

Bit Field 0BPSEL

BPSEL

Type r w rw

F7HHWBPDR Reset: 00H

Hardware Breakpoints Data Register

Bit Field HWBPxx

Type rw

Table 14 SSC Register Overview

,/ Infineon

XC866

Functional Description

Data Sheet 38 V1.2, 2007-10

3.3 Flash Memory

The Flash memory provides an embedded user-programmable non-volatile memory,

allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V

supply from the Embedded Voltage Regulator (EVR) and does not require additional

programming or erasing voltage. The sectorization of the Flash memory allows each

sector to be erased independently.

Features

• In-System Programming (ISP) via UART

• In-Application Programming (IAP)

• Error Correction Code (ECC) for dynamic correction of single-bit errors

• Background program and erase operations for CPU load minimization

• Support for aborting erase operation

• Minimum program width1) of 32-byte for D-Flash and 32-byte for P-Flash

• 1-sector minimum erase width

• 1-byte read access

• Flash is delivered in erased state (read all zeros)

• Operating supply voltage: 2.5 V ± 7.5 %

• Read access time: 3 × tCCLK = 112.5 ns2)

• Program time: 209440 / fSYS = 2.6 ms3)

• Erase time: 8175360 / fSYS =102 ms

1) P-Flash: 32-byte wordline can only be programmed once, i.e., one gate disturb allowed.

D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed.

2) fsys =80MHz±7.5% (fCCLK = 26.7 MHz ± 7.5 %) is the maximum frequency range for Flash read access.

3) fsys = 80 MHz ± 7.5% is the only frequency range for Flash programming and erasing. fsysmin is used for

obtaining the worst case timing.

Inflneon ca” 2) 2)

XC866

Functional Description

Data Sheet 39 V1.2, 2007-10

Table 16 shows the Flash data retention and endurance targets.

3.3.1 Flash Bank Sectorization

The XC866 product family offers four Flash devices with either 8 Kbytes or 16 Kbytes of

embedded Flash memory. These Flash memory sizes are made up of two or four

4-Kbyte Flash banks, respectively. Each Flash device consists of Program Flash

(P-Flash) bank(s) and a single Data Flash (D-Flash) bank with different sectorization

shown in Figure 11. Both types can be used for code and data storage. The label “Data”

neither implies that the D-Flash is mapped to the data memory region, nor that it can only

be used for data storage. It is used to distinguish the different Flash bank sectorizations.

The XC866 ROM devices offer a single 4-Kbyte D-Flash bank.

Table 16 Flash Data Retention and Endurance (Operating Conditions apply)

Retention Endurance1)

1) One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance

data specified in Table 16 is valid only if the following conditions are fulfilled:

- the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles.

- the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles.

- the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles.

Size Remarks

Program Flash

20 years 1,000 cycles up to 16 Kbytes2)

2) If no Flash is used for data, the Program Flash size can be up to the maximum Flash size available in the

device variant. Having more Data Flash will mean less Flash is available for Program Flash.

for 16-Kbyte Variant

20 years 1,000 cycles up to 8 Kbytes2) for 8-Kbyte Variant

20 years 1,000 cycles up to 4 Kbytes2) for 4-Kbyte Variant

Data Flash

20 years 1,000 cycles 4 Kbytes

5 years 10,000 cycles 1 Kbyte

2 years 70,000 cycles 512 bytes

2 years 100,000 cycles 128 bytes

n/ Infineon

XC866

Functional Description

Data Sheet 40 V1.2, 2007-10

Figure 11 Flash Bank Sectorization

The internal structure of each Flash bank represents a sector architecture for flexible

erase capability. The minimum erase width is always a complete sector, and sectors can

be erased separately or in parallel. Contrary to standard EPROMs, erased Flash

memory cells contain 0s.

The D-Flash bank is divided into more physical sectors for extended erasing and

reprogramming capability; even numbers for each sector size are provided to allow

greater flexibility and the ability to adapt to a wide range of application requirements.

Sector 9: 128-byte

Sector 5: 256-byte

Sector 3: 512-byte

Sector 1: 1-Kbyte

Sector 0: 1-Kbyte

Sector 7: 128-byte

Sector 8: 128-byte

Sector 6: 128-byte

Sector 4: 256-byte

Sector 2: 512-byte

Sector 0: 3.75-Kbyte

P-Flash D-Flash

Sector 2: 128-byte

Sector 1: 128-byte

Inflneon _1111 1m", New; fauna uuuu H ‘,

XC866

Functional Description

Data Sheet 41 V1.2, 2007-10

3.3.2 Flash Programming Width

For the P-Flash banks, a programmed wordline (WL) must be erased before it can be

reprogrammed as the Flash cells can only withstand one gate disturb. This means that

the entire sector containing the WL must be erased since it is impossible to erase a

single WL.

For the D-Flash bank, the same WL can be programmed twice before erasing is required

as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to

program the same WL, for example, with 16 bytes of data in two times (see Figure 12).

Figure 12 D-Flash Programming

Note: When programming a D-Flash WL the second time, the previously programmed

Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain

its original contents and to prevent “over-programming”.

0000 ….. 0000

32 bytes (1 WL)

1111 ….. 1111

0000 ….. 0000

16 bytes 16 bytes

0000 ….. 0000

1111 ….. 1111

Flash memory cells 32-byte write buffers

1111 ….. 0000

1111 ….. 1111

0000 ….. 0000

1111 ….. 0000

Program 1

Program 2

Note: A Flash memory cell can be programmed

from 0 to 1, but not from 1 to 0.

Inflneon

XC866

Functional Description

Data Sheet 42 V1.2, 2007-10

3.4 Interrupt System

The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt

requests. In addition to the standard interrupt functions supported by the core, e.g.,

configurable interrupt priority and interrupt masking, the XC866 interrupt system

provides extended interrupt support capabilities such as the mapping of each interrupt

vector to several interrupt sources to increase the number of interrupt sources

supported, and additional status registers for detecting and determining the interrupt

source.

3.4.1 Interrupt Source

Figure 13 to Figure 17 give a general overview of the interrupt sources and illustrates

the request and control flags.

Figure 13 Non-Maskable Interrupt Request Sources

0073 H

NMIWDT

NMICON.0

WDT Overflow

>=1

Non

Maskable

Interrupt

NMIPLL

NMICON.1

PLL Loss of Lock

NMIFLASH

Flash Operation

Complete

NMIVDD

NMICON.4

VDD Pre-Warning

FNMIWDT

NMIISR.0

FNMIPLL

NMIISR.1

FNMIFLASH

NMIISR.2

FNMIVDD

NMIISR.4

NMIVDDP

NMICON.5

VDDP Pre-Warning FNMIVDDP

NMIISR.5

NMIECC

NMICON.6

Flash ECC Error FNMIECC

NMIISR.6

0/ Infineon

XC866

Functional Description

Data Sheet 43 V1.2, 2007-10

Figure 14 Interrupt Request Sources (Part 1)

Highest

Lowest

Priority Level

Bit-addressable

Request flag is cleared by hardware

000B H

ET0

IEN0.1

TF0

TCON.5

Timer 0

Overflow

001B H

ET1

IEN0.3

TF1

TCON.7

Timer 1

Overflow

IP.1/

IPH.1

IP.3/

IPH.3

0023 H

IEN0.4 IP.4/

IPH.4

>=1

SCON.0

SCON.1

UART

Transmit

0003 H

EX0

IEN0.0

IE0

TCON.1

IP.0/

IPH.0

0013 HIP.2/

IPH.2

IT0

TCON.0

EX1

IEN0.2

IE1

TCON.3

IT1

TCON.2

IEN0.7

UART

Receive

EXINT0

EXICON0.0/1

EINT0

EXINT1

EXICON0.2/3

EINT1

EXINT0

IRCON0.0

EXINT1

IRCON0.1

Infineon

XC866

Functional Description

Data Sheet 44 V1.2, 2007-10

Figure 15 Interrupt Request Sources (Part 2)

Bit-addressable

Request flag is cleared by hardware

Highest

Lowest

Priority Level

Bit-addressable

Request flag is cleared by hardware

0043 H

EX2

IEN1.2 IP1.2/

IPH1.2

EXINT2

EXICON0.4/5

EXINT2

IRCON0.2

EINT2

002B H

ET2

IEN0.5 IP.5/

IPH.5

>=1

TF2

EXF2

Timer 2

Overflow

EXEN2

T2EX

IEN0.7

004B H

EXM

IEN1.3 IP1.3/

IPH1.3

>=1

EXINT5

EXICON1.2/3

EXINT5

IRCO N0.5

EINT5

EXINT4

EXICON1.0/1

EXINT4

IRCO N0.4

EINT4

EXINT3

EXICON0.6/7

EXINT3

IRCO N0.3

EINT3

EXINT6

EXICON1.4/5

EXINT6

IRCO N0.6

EINT6

EDGES

T2MOD.5 NDOV

FDCON.2

Normal Divider

Overf low

FDCON.6

EOFSYN

FDCON.4

End of

Synch Byte

ERRSYN

Synch Byte

Error

SYNEN

>=1

FDCON.5

T2_T2CON.7

T2_T2CON.6

T2_T2CON.3

FDCON.6

Inflneon

XC866

Functional Description

Data Sheet 45 V1.2, 2007-10

Figure 16 Interrupt Request Sources (Part 3)

IEN0.7

Highest

Lowest

Priority Level

Bit-addressable

Request flag is cleared by hardware

003B H

ESSC

IEN1.1 IP1.1/

IPH1.1

>=1TIR

IRCON1.1

RIR

IRCON1.2

EIR

IRCON1.0

SSC Error

SSC Transmit

SSC Receive

0033 H

EADC

IEN1.0 IP1.0/

IPH1.0

>=1

ADCSRC0

IRCON1.3

ADC Service

Request 0

ADC Service

Request 1 ADCSRC1

IRCON1.4

0053 H

CCU6 Node 0

IP1.4/

IPH1.4

005B H

CCU6 Node 1

IP1.5/

IPH1.5

0063 H

CCU6 Node 2

IP1.6/

IPH1.6

006B H

CCU6 Node 3

IP1.7/

IPH1.7

ECCIP0

IEN1.4

ECCIP1

IEN1.5

ECCIP2

IEN1.6

ECCIP3

IEN1.7

CCU6SR0

IRCON3.0

CCU6SR1

IRCON3.4

CCU6SR2

IRCON4.0

CCU6SR3

IRCON4.4

Inflneon

XC866

Functional Description

Data Sheet 46 V1.2, 2007-10

Figure 17 Interrupt Request Sources (Part 4)

CCU6 Interrupt node

>=1

CC60 ENCC60R

IENL.0

ICC60R

ISL.0

ENCC60F

IENL.1

ICC60F

ISL.1 INPL.1 INPL.0

>=1

CC61 ENCC61R

IENL.2

ICC61R

ISL.2

ENCC61F

IENL.3

ICC61F

ISL.3 INPL.3 INPL.2

>=1

CC62 ENCC62R

IENL.4

ICC62R

ISL.4

ENCC62F

IENL.5

ICC62F

ISL.5 INPL.5 INPL.4

>=1

ENT12OM

IENL.6

T12OM

ISL.6

ENT12PM

IENL.7

T12PM

ISL.7 INPH.3 INPH.2

>=1

ENT13CM

IENH.0

T13CM

ISH.0

ENT13PM

IENH.1

T13PM

ISH.1 INPH.5 INPH.4

>=1

ENTRPF

IENH.2

TRPF

ISH.2

ENWHE

IENH.5

WHE

ISH.5 INPH.1 INPH.0

T12

One match

T12

Period match

T13

Compare match

T13

Period match

CTRAP

Wrong Hall

Event

INPL.7 INPL.6

ENCHE

IENH.4

CHE

ISH.4

Correct Hall

Event

>=1

ENSTR

IENH.7

STR

ISH.7

Multi-Channel

Shadow

Transfer

n/ Infineon

XC866

Functional Description

Data Sheet 47 V1.2, 2007-10

3.4.2 Interrupt Source and Vector

Each interrupt source has an associated interrupt vector address. This vector is

accessed to service the corresponding interrupt source request. The interrupt service of

each interrupt source can be individually enabled or disabled via an enable bit. The

assignment of the XC866 interrupt sources to the interrupt vector addresses and the

corresponding interrupt source enable bits are summarized in Table 17.

Table 17 Interrupt Vector Addresses

Interrupt

Source

Vector

Address

Assignment for XC866 Enable Bit SFR

NMI 0073HWatchdog Timer NMI NMIWDT NMICON

PLL NMI NMIPLL

Flash NMI NMIFLASH

VDDC Prewarning NMI NMIVDD

VDDP Prewarning NMI NMIVDDP

Flash ECC NMI NMIECC

XINTR0 0003HExternal Interrupt 0 EX0 IEN0

XINTR1 000BHTimer 0 ET0

XINTR2 0013HExternal Interrupt 1 EX1

XINTR3 001BHTimer 1 ET1

XINTR4 0023HUART ES

XINTR5 002BHT2 ET2

Fractional Divider

(Normal Divider Overflow)

LIN

n/ Infineon

XC866

Functional Description

Data Sheet 48 V1.2, 2007-10

XINTR6 0033HADC EADC IEN1

XINTR7 003BHSSC ESSC

XINTR8 0043HExternal Interrupt 2 EX2

XINTR9 004BHExternal Interrupt 3 EXM

External Interrupt 4

External Interrupt 5

External Interrupt 6

XINTR10 0053HCCU6 INP0 ECCIP0

XINTR11 005BHCCU6 INP1 ECCIP1

XINTR12 0063HCCU6 INP2 ECCIP2

XINTR13 006BHCCU6 INP3 ECCIP3

Table 17 Interrupt Vector Addresses (cont’d)

n/ Infineon

XC866

Functional Description

Data Sheet 49 V1.2, 2007-10

3.4.3 Interrupt Priority

Each interrupt source, except for NMI, can be individually programmed to one of the four

possible priority levels. The NMI has the highest priority and supersedes all other

interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are

available to program the priority level of each non-NMI interrupt vector.

A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another

interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot

be interrupted by any other interrupt source.

If two or more requests of different priority levels are received simultaneously, the

request of the highest priority is serviced first. If requests of the same priority are

received simultaneously, then an internal polling sequence determines which request is

serviced first. Thus, within each priority level, there is a second priority structure

determined by the polling sequence shown in Table 18.

Table 18 Priority Structure within Interrupt Level

Source Level

Non-Maskable Interrupt (NMI) (highest)

External Interrupt 0 1

Timer 0 Interrupt 2

External Interrupt 1 3

Timer 1 Interrupt 4

UART Interrupt 5

Timer 2,Fractional Divider, LIN Interrupts 6

ADC Interrupt 7

SSC Interrupt 8

External Interrupt 2 9

External Interrupt [6:3] 10

CCU6 Interrupt Node Pointer 0 11

CCU6 Interrupt Node Pointer 1 12

CCU6 Interrupt Node Pointer 2 13

CCU6 Interrupt Node Pointer 3 14

,/ Infineon

XC866

Functional Description

Data Sheet 50 V1.2, 2007-10

3.5 Parallel Ports

The XC866 has 27 port pins organized into four parallel ports, Port 0 (P0) to Port 3 (P3).

Each pin has a pair of internal pull-up and pull-down devices that can be individually

enabled or disabled. Ports P0, P1 and P3 are bidirectional and can be used as general

purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip

peripherals. When configured as an output, the open drain mode can be selected. Port

P2 is an input-only port, providing general purpose input functions, alternate input

functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital

Converter (ADC).

Bidirectional Port Features:

• Configurable pin direction

• Configurable pull-up/pull-down devices

• Configurable open drain mode

• Transfer of data through digital inputs and outputs (general purpose I/O)

• Alternate input/output for on-chip peripherals

Input Port Features:

• Configurable input driver

• Configurable pull-up/pull-down devices

• Receive of data through digital input (general purpose input)

• Alternate input for on-chip peripherals

• Analog input for ADC module

infineon §k W

XC866

Functional Description

Data Sheet 51 V1.2, 2007-10

Figure 18 General Structure of Bidirectional Port

Px_OD

Open Drain

Control Register

Px_Data

Data Register

Internal Bus

AltDataOut 2

Px_ALTSEL0

Alternate Select

Px_ALTSEL1

Alternate Select

AltDataIn

Px_PUDEN

Pull-up/Pull-down

Enable Register

Px_PUDSEL

Pull-up/Pull-down

Select Register

AltDataOut1

Pad

Out

Output

Driver

Input

Driver

Schmitt Trigger

enable

Pull

Device

Pull

Down

Device

VDDP

enable

Px_DIR

Direction Register

AltDataOut 3

0/ Infineon ,T ‘ {I v.9 a?

XC866

Functional Description

Data Sheet 52 V1.2, 2007-10

Figure 19 General Structure of Input Port

Px_ DATA

Data Register

Internal Bus

AltDataIn

Px_PUDEN

Pull-up/Pull-down

Enable Regist er

Px_PUDSEL

Pull-up/Pull-down

Select Register

Input

Dri ver

Schmitt Trigger

AnalogIn

Px_DIR

Direct ion Regist er

Pad

Pull

Device

Pull

Down

Device

VDDP

enable

Infineon

XC866

Functional Description

Data Sheet 53 V1.2, 2007-10

3.6 Power Supply System with Embedded Voltage Regulator

The XC866 microcontroller requires two different levels of power supply:

• 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports

• 2.5 V for the core, memory, on-chip oscillator, and peripherals

Figure 20 shows the XC866 power supply system. A power supply of 3.3 V or 5.0 V

must be provided from the external power supply pin. The 2.5 V power supply for the

logic is generated by the EVR. The EVR helps to reduce the power consumption of the

whole chip and the complexity of the application board design.

The EVR consists of a main voltage regulator and a low power voltage regulator. In

active mode, both voltage regulators are enabled. In power-down mode, the main

voltage regulator is switched off, while the low power voltage regulator continues to

function and provide power supply to the system with low power consumption.

Figure 20 XC866 Power Supply System

EVR Features:

• Input voltage (VDDP): 3.3 V/5.0 V

• Output voltage (VDDC): 2.5 V ± 7.5%

• Low power voltage regulator provided in power-down mode

•VDDC and VDDP prewarning detection

•VDDC brownout detection

On-chip

OSC

CPU &

Memory

DDC

(2.5V)

DDP

(3.3V/5.0V)

SSP

GPIO

Ports

(P0-P3)

EVR

Peripheral

logic

FLASH

ADC

PLL

XTAL 1&

XTAL 2

/ infineon

XC866

Functional Description

Data Sheet 54 V1.2, 2007-10

3.7 Reset Control

The XC866 has five types of reset: power-on reset, hardware reset, watchdog timer

reset, power-down wake-up reset, and brownout reset.

When the XC866 is first powered up, the status of certain pins (see Table 20) must be

defined to ensure proper start operation of the device. At the end of a reset sequence,

the sampled values are latched to select the desired boot option, which cannot be

modified until the next power-on reset or hardware reset. This guarantees stable

conditions during the normal operation of the device.

In order to power up the system properly, the external reset pin RESET must be asserted

until VDDC reaches 0.9*VDDC. The delay of external reset can be realized by an external

capacitor at RESET pin. This capacitor value must be selected so that VRESET reaches

0.4 V, but not before VDDC reaches 0.9* VDDC.

A typical application example is shown in Figure 21. VDDP capacitor value is 300 nF.

VDDC capacitor value is 220 nF. The capacitor connected to RESET pin is 100 nF.

Typically, the time taken for VDDC to reach 0.9*VDDC is less than 50 µs once VDDP

reaches 2.3V. Hence, based on the condition that 10% to 90% VDDP (slew rate) is less

than 500 µs, the RESET pin should be held low for 500 µs typically. See Figure 22.

Figure 21 Reset Circuitry

VSSP VDDP VDDC VSSC

3.3V/5V

RESET

EVR

e.g. 300nF 220nF

typ.

100nF

XC866

30k

\ @ineon

XC866

Functional Description

Data Sheet 55 V1.2, 2007-10

Figure 22 VDDP, VDDC and VRESET during Power-on Reset

The second type of reset in XC866 is the hardware reset. This reset function can be used

during normal operation or when the chip is in power-down mode. A reset input pin

RESET is provided for the hardware reset. To ensure the recognition of the hardware

reset, pin RESET must be held low for at least 100 ns.

The Watchdog Timer (WDT) module is also capable of resetting the device if it detects

a malfunction in the system.

Another type of reset that needs to be detected is a reset while the device is in

power-down mode (wake-up reset). While the contents of the static RAM are undefined

after a power-on reset, they are well defined after a wake-up reset from power-down

mode.

VDDP

RESET wit

capacitor

2.3V VDDC

< 0.4V

0.9*VDDC

2.5V

Voltage

Time

typ. < 50 us

Inflneon e”

XC866

Functional Description

Data Sheet 56 V1.2, 2007-10

3.7.1 Module Reset Behavior

Table 19 shows how the functions of the XC866 are affected by the various reset types.

A “ ” means that this function is reset to its default state.

3.7.2 Booting Scheme

When the XC866 is reset, it must identify the type of configuration with which to start the

different modes once the reset sequence is complete. Thus, boot configuration

information that is required for activation of special modes and conditions needs to be

applied by the external world through input pins. After power-on reset or hardware reset,

the pins MBC, TMS and P0.0 collectively select the different boot options. Table 20

shows the available boot options in the XC866.

Table 19 Effect of Reset on Device Functions

Module/

Function

Wake-Up

Reset

Watchdog

Reset

Hardware

Reset

Power-On

Reset

Brownout

Reset

CPU Core

Peripherals

On-Chip

Static RAM

Not affected,

reliable

Not affected,

reliable

Not affected,

reliable

Affected, un-

reliable

Affected, un-

reliable

Oscillator,

PLL

Not affected

Port Pins

EVR The voltage

regulator is

switched on

Not affected

FLASH

NMI Disabled Disabled

Table 20 XC866 Boot Selection

MBC TMS P0.0 Type of Mode PC Start Value

1 0 x User Mode; on-chip OSC/PLL non-bypassed 0000H

0 0 x BSL Mode; on-chip OSC/PLL non-bypassed 0000H

010 OCDS Mode

1); on-chip OSC/PLL non-

bypassed

1) The OCDS mode is not accessible if Flash is protected.

0000H

1 1 0 Standalone User (JTAG) Mode2); on-chip

OSC/PLL non-bypassed (normal)

2) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.

0000H

0/ Infineon DE

XC866

Functional Description

Data Sheet 57 V1.2, 2007-10

3.8 Clock Generation Unit

The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the

XC866. The power consumption is indirectly proportional to the frequency, whereas the

performance of the microcontroller is directly proportional to the frequency. During user

program execution, the frequency can be programmed for an optimal ratio between

performance and power consumption. Therefore the power consumption can be

adapted to the actual application state.

Features:

• Phase-Locked Loop (PLL) for multiplying clock source by different factors

• PLL Base Mode

• Prescaler Mode

• PLL Mode

• Power-down mode support

The CGU consists of an oscillator circuit and a PLL.In the XC866, the oscillator can be

from either of these two sources: the on-chip oscillator (10 MHz) or the external oscillator

(4 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip oscillator and

external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be

used by default.The external oscillator can be selected via software. In addition, the PLL

provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows

emergency routines to be executed for system recovery or to perform system shut down.

Figure 23 CGU Block Diagram

PLL

core

lock

detect

N:1

P:1

fvco

osc fail

detect

OSC fosc

K:1

fsys

NDIV

OSCR

LOCK

VCOBYP

OSCDISC

n/ Infineon

XC866

Functional Description

Data Sheet 58 V1.2, 2007-10

The clock system provides three ways to generate the system clock:

PLL Base Mode

The system clock is derived from the VCO base (free running) frequency clock divided

by the K factor.

Prescaler Mode (VCO Bypass Operation)

In VCO bypass operation, the system clock is derived from the oscillator clock, divided

by the P and K factors.

PLL Mode

The system clock is derived from the oscillator clock, multiplied by the N factor, and

divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for

this PLL mode. The PLL mode is used during normal system operation. .

Table 3-1 shows the settings of bits OSCDISC and VCOBYP for different clock mode

selection.

Note: When oscillator clock is disconnected from PLL, the clock mode is PLL Base mode

regardless of the setting of VCOBYP bit.

System Frequency Selection

For the XC866, the values of P and K are fixed to “1” and “2”, respectively. In order to

obtain the required system frequency, fsys, the value of N can be selected by bit NDIV

for different oscillator inputs. Table 21 provides examples on how fsys = 80 MHz can be

obtained for the different oscillator sources.

Table 3-1 Clock Mode Selection

OSCDISC VCOBYP Clock Working Modes

0 0 PLL Mode

01Prescaler Mode

1 0 PLL Base Mode

1 1 PLL Base Mode

fSYS fVCObase

----

×=

fSYS fOSC

PK×

-------------

×=

fSYS fOSC

PK×

-------------

×=

n/ Infineon

XC866

Functional Description

Data Sheet 59 V1.2, 2007-10

Table 22 shows the VCO range for the XC866.

3.8.1 Recommended External Oscillator Circuits

The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal

oscillator or an external stable clock source. It basically consists of an inverting amplifier

and a feedback element with XTAL1 as input, and XTAL2 as output.

When using a crystal, a proper external oscillator circuitry must be connected to both

pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz

to 12 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and

depending on the crystal type, a series resistor RX2, to limit the current. A test resistor

RQ may be temporarily inserted to measure the oscillation allowance (negative

resistance) of the oscillator circuitry. RQ values are typically specified by the crystal

vendor. The CX1 and CX2 values shown in Figure 24 can be used as starting points for

the negative resistance evaluation and for non-productive systems. The exact values

and related operating range are dependent on the crystal frequency and have to be

determined and optimized together with the crystal vendor using the negative resistance

method. Oscillation measurement with the final target system is strongly recommended

to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance

(margin negative resistance) for the oscillator-crystal system.

When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is

left open (unconnected).

The oscillator can also be used in combination with a ceramic resonator. The final

circuitry must also be verified by the resonator vendor.

Figure 24 shows the recommended external oscillator circuitries for both operating

modes, external crystal mode and external input clock mode.

Table 21 System frequency (fsys =80MHz)

Oscillator fosc N P K fsys

On-chip 10 MHz 16 1 2 80 MHz

External 10 MHz 16 1 2 80 MHz

8 MHz 20 1 2 80 MHz

5 MHz 32 1 2 80 MHz

Table 22 VCO Range

fVCOmin fVCOmax fVCOFREEmin fVCOFREEmax Unit

150 200 20 80 MHz

100 150 10 80 MHz

n/ Infineon En L,

XC866

Functional Description

Data Sheet 60 V1.2, 2007-10

Figure 24 External Oscillator Circuitries

Note: For crystal operation, it is strongly recommended to measure the negative

resistance in the final target system (layout) to determine the optimum parameters

for the oscillator operation. Please refer to the minimum and maximum values of

the negative resistance specified by the crystal supplier.

Clock_EXOSC

XC866

Oscillator

4 - 12

MHz

XTAL1

XTAL2

XC866

Oscillator

XTAL1

XTAL2

External Clock

Signal

OSC

Fundamental

Mode Crystal

Crystal Frequency C

, C

4 MHz

8 MHz

10 MHz

12 MHz 12 pF

15 pF

18 pF

33 pF

1) Note that these are evaluation start values!

0/ Infineon

XC866

Functional Description

Data Sheet 61 V1.2, 2007-10

3.8.2 Clock Management

The CGU generates all clock signals required within the microcontroller from a single

clock, fsys. During normal system operation, the typical frequencies of the different

modules are as follow:

• CPU clock: CCLK, SCLK = 26.7 MHz

• CCU6 clock: FCLK = 26.7 MHz

• Other peripherals: PCLK = 26.7 MHz

• Flash Interface clock: CCLK3 = 80 MHz and CCLK = 26.7 MHz

In addition, different clock frequency can output to pin CLKOUT(P0.0). The clock output

frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), the

resulting output frequency has 50% duty cycle. Figure 25 shows the clock distribution of

the XC866.

Figure 25 Clock Generation from fsys

PLL

N,P,K

fsys

CLKREL

FCLK

CCLK

SCLK

PCLK

CCU6

CORE

Peripherals

OSC

fosc

FLASH

Interface

CCLK3

CLKOUT

COREL

COUTS

Toggle

Latch

TLEN

0/ Infineon

XC866

Functional Description

Data Sheet 62 V1.2, 2007-10

For power saving purposes, the clocks may be disabled or slowed down according to

Table 23.

Table 23 System frequency (fsys =80MHz)

Power Saving Mode Action

Idle Clock to the CPU is disabled.

Slow-down Clocks to the CPU and all the peripherals, including CCU6, are

divided by a common programmable factor defined by bit field

CMCON.CLKREL.

Power-down Oscillator and PLL are switched off.

Inflneon

XC866

Functional Description

Data Sheet 63 V1.2, 2007-10

3.9 Power Saving Modes

The power saving modes of the XC866 provide flexible power consumption through a

combination of techniques, including:

• Stopping the CPU clock

• Stopping the clocks of individual system components

• Reducing clock speed of some peripheral components

• Power-down of the entire system with fast restart capability

After a reset, the active mode (normal operating mode) is selected by default (see

Figure 26) and the system runs in the main system clock frequency. From active mode,

different power saving modes can be selected by software. They are:

• Idle mode

• Slow-down mode

• Power-down mode

Figure 26 Transition between Power Saving Modes

POWER-DOWN

IDLE

ACTIVE

SLOW-DOWN

set PD

bit

set PD

bit

set IDLE

bit

set IDLE

bit

set SD

bit

clear SD

bit

any interrupt

& SD=0

EXINT0/RXD pin

& SD=0

EXINT0/RXD pin

& SD=1

any interrupt

& SD=1

0/ Infineon W;

XC866

Functional Description

Data Sheet 64 V1.2, 2007-10

3.10 Watchdog Timer

The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and

recover from software or hardware failures. The WDT is reset at a regular interval that is

predefined by the user. The CPU must service the WDT within this interval to prevent the

WDT from causing an XC866 system reset. Hence, routine service of the WDT confirms

that the system is functioning properly. This ensures that an accidental malfunction of

the XC866 will be aborted in a user-specified time period. In debug mode, the WDT is

suspended and stops counting. Therefore, there is no need to refresh the WDT during

debugging.

Features:

• 16-bit Watchdog Timer

• Programmable reload value for upper 8 bits of timer

• Programmable window boundary

• Selectable input frequency of fPCLK/2 or fPCLK/128

• Time-out detection with NMI generation and reset prewarning activation (after which

a system reset will be performed)

The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This

16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT

can be preset to a user-programmable value via a watchdog service access in order to

modify the watchdog expire time period. The lower 8 bits are reset on each service

access. Figure 27 shows the block diagram of the WDT unit.

Figure 27 WDT Block Diagram

WDTREL

MUX

WDT Low Byte

1:2 Clear

WDT

Control

1:128

WDT High Byte

WDTTO

WDTIN

PCLK

Logic

ENWDT

ENWDT_P

WDTRS

Overflow/Time-out Control &

Window-boundary control

WDTWINB

@ineon

XC866

Functional Description

Data Sheet 65 V1.2, 2007-10

If the WDT is not serviced before the timer overflow, a system malfunction is assumed.

As a result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is

entered. The prewarning period lasts for 30H count, after which the system is reset

(assert WDTRST).

The WDT has a “programmable window boundary” which disallows any refresh during

the WDT’s count-up. A refresh during this window boundary constitutes an invalid

access to the WDT, causing the reset prewarning to be entered but without triggering the

WDT NMI. The system will still be reset after the prewarning period is over. The window

boundary is from 0000H to the value obtained from the concatenation of WDTWINB and

00H.

After being serviced, the WDT continues counting up from the value (<WDTREL> * 28).

The time period for an overflow of the WDT is programmable in two ways:

• the input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128

• the reload value WDTREL for the high byte of WDT can be programmed in register

WDTREL

The period, PWDT, between servicing the WDT and the next overflow can be determined

by the following formula:

If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT

between servicing the WDT and the next overflow is shortened if WDTWINB is greater

than WDTREL, see Figure 28. This period can be calculated using the same formula by

replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB should not

be smaller than WDTREL.

Figure 28 WDT Timing Diagram

PWDT

21WDTIN+6×()

216 WDTREL–2

×()×

fPCLK

------------------------------------------------------------------------------------------------------=

WDTREL

WDTWINB

time

Count

FFFF

No refresh

allowed Refresh allowed

n/ Infineon

XC866

Functional Description

Data Sheet 66 V1.2, 2007-10

Table 24 lists the possible watchdog time range that can be achieved for different

module clock frequencies . Some numbers are rounded to 3 significant digits.

Table 24 Watchdog Time Ranges

Reload value

in WDTREL

Prescaler for fPCLK

2 (WDTIN = 0) 128 (WDTIN = 1)

26.7 MHz 26.7 MHz

FFH19.2 µs1.23 ms

7FH2.48 ms 159 ms

00H4.92 ms 315 ms

n/ Infineon

XC866

Functional Description

Data Sheet 67 V1.2, 2007-10

3.11 Universal Asynchronous Receiver/Transmitter

The Universal Asynchronous Receiver/Transmitter (UART) provides a full-duplex

asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is

also receive-buffered, i.e., it can commence reception of a second byte before a

previously received byte has been read from the receive register. However, if the first

byte still has not been read by the time reception of the second byte is complete, one of

the bytes will be lost.

Features:

• Full-duplex asynchronous modes

– 8-bit or 9-bit data frames, LSB first

– fixed or variable baud rate

• Receive buffered

• Multiprocessor communication

• Interrupt generation on the completion of a data transmission or reception

The UART can operate in the four modes as shown in Table 25. Data is transmitted on

TXD and received on RXD.

There are several ways to generate the baud rate clock for the serial port, depending on

the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at

fPCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock

and can be configured to either fPCLK/32 or fPCLK/64. The variable baud rate is set by

either the underflow rate on the dedicated baud-rate generator, or by the overflow rate

on Timer 1.

Table 25 UART Modes

Operating Mode Baud Rate

Mode 0: 8-bit shift register fPCLK/2

Mode 1: 8-bit shift UART Variable

Mode 2: 9-bit shift UART fPCLK/32 or fPCLK/64

Mode 3: 9-bit shift UART Variable

0/ Infineon |:F |:F D

XC866

Functional Description

Data Sheet 68 V1.2, 2007-10

3.11.1 Baud-Rate Generator

The baud-rate generator is based on a programmable 8-bit reload value, and includes

divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud

rates based on its input clock fPCLK, see Figure 29.

Figure 29 Baud-rate Generator Circuitry

The baud rate timer is a count-down timer and is clocked by either the output of the

fractional divider (fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the

output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate

generation, the fractional divider must be configured to fractional divider mode

(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start

or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit

reload value in register BG and one clock pulse is generated for the serial channel.

Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the

baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12.

The baud rate (fBR) value is dependent on the following parameters:

• Input clock fPCLK

• Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON

• Fractional divider (STEP/256) defined by register FDSTEP

(to be considered only if fractional divider is enabled and operating in fractional divider

mode)

FDSTEP

FDM

Adder

FDRES

FDEN&FDM

clk

Fractional Divider

Prescaler

NDOV

‘0’

FDEN

(overflow)

8-Bit Baud Rate Timer

8-Bit Reload Value

DIV

PCL K

MOD

n/ Infineon

XC866

Functional Description

Data Sheet 69 V1.2, 2007-10

• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG

The following formulas calculate the final baud rate without and with the fractional divider

respectively:

The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module

clock of 26.7 MHz, the maximum achievable baud rate is 0.83 MBaud.

Standard LIN protocal can support a maximum baud rate of 20kHz, the baud rate

accuracy is not critical and the fractional divider can be disabled. Only the prescaler is

used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of

20kHz to 115.2kHz, the higher baud rates require the use of the fractional divider for

greater accuracy.

Table 26 lists the various commonly used baud rates with their corresponding parameter

settings and deviation errors. The fractional divider is disabled and a module clock of

26.7 MHz is used.

The fractional divider allows baud rates of higher accuracy (lower deviation error) to be

generated. Table 27 lists the resulting deviation errors from generating a baud rate of

Table 26 Typical Baud rates for UART with Fractional Divider disabled

Baud rate Prescaling Factor

(2BRPRE)

Reload Value

(BR_VALUE + 1)

Deviation Error

19.2 kBaud 1 (BRPRE=000B) 87 (57H) -0.22 %

9600 Baud 1 (BRPRE=000B)174 (AE

H) -0.22 %

4800 Baud 2 (BRPRE=001B)174 (AE

H) -0.22 %

2400 Baud 4 (BRPRE=010B)174 (AE

H) -0.22 %

baud rate fPCLK

16 2BRPRE BR_VALUE 1+()××

----------------------------------------------------------------------------------- where 2BRPRE BR_VALUE 1+()1>×=

baud rate fPCLK

16 2BRPRE BR_VALUE 1+()××

----------------------------------------------------------------------------------- STEP

256

---------------

×=

n/ Infineon

XC866

Functional Description

Data Sheet 70 V1.2, 2007-10

115.2 kHz, using different module clock frequencies. The fractional divider is enabled

(fractional divider mode) and the corresponding parameter settings are shown.

Table 27 Deviation Error for UART with Fractional Divider enabled

fPCLK Prescaling Factor

(2BRPRE)

Reload Value

(BR_VALUE + 1)

STEP Deviation

Error

26.67 MHz 1 10 (AH) 177 (B1H) +0.03 %

13.33 MHz 1 7 (7H)248 (F8

H) +0.11 %

6.67 MHz 1 3 (3H)212 (D4

H) -0.16 %

,/ Infineon

XC866

Functional Description

Data Sheet 71 V1.2, 2007-10

3.11.2 Baud Rate Generation using Timer 1

In UART modes 1 and 3, Timer 1 can be used for generating the variable baud rates. In

theory, this timer could be used in any of its modes. But in practice, it should be set into

auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the

required baud rate. The baud rate is determined by the Timer 1 overflow rate and the

value of SMOD as follows:

[3.1]

3.12 Normal Divider Mode (8-bit Auto-reload Timer)

Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider

mode, while at the same time disables baud rate generation (see Figure 29). Once the

fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with

no relation to baud rate generation) and counts up from the reload value with each input

clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit

field STEP in register FDSTEP defines the reload value. At each timer overflow, an

overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives

an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP.

The output frequency in normal divider mode is derived as follows:

[3.2]

Mode 1, 3 baud rate 2SMOD fPCLK

32 2 256 TH1–()××

-----------------------------------------------------=

fMOD fDIV

256 STEP–

------------------------------

×=

0/ Infineon iﬂ/WWW ﬁhmﬁmﬂ

XC866

Functional Description

Data Sheet 72 V1.2, 2007-10

3.13 LIN Protocol

The UART can be used to support the Local Interconnect Network (LIN) protocol for both

master and slave operations. The LIN baud rate detection feature provides the capability

to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be

synchronized to the LIN baud rate for data transmission and reception.

LIN is a holistic communication concept for local interconnected networks in vehicles.

The communication is based on the SCI (UART) data format, a single-master/multiple-

slave concept, a clock synchronization for nodes without stabilized time base. An

attractive feature of LIN is self-synchronization of the slave nodes without a crystal or

ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the

baud rate must be calculated and returned with every message frame.

The structure of a LIN frame is shown in Figure 30. The frame consists of the:

• header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field

• response time

• data bytes (according to UART protocol)

• checksum

Figure 30 Structure of LIN Frame

3.13.1 LIN Header Transmission

LIN header transmission is only applicable in master mode. In the LIN communication,

a master task decides when and which frame is to be transferred on the bus. It also

identifies a slave task to provide the data transported by each frame. The information

needed for the handshaking between the master and slave tasks is provided by the

master task through the header portion of the frame.

The header consists of a break and synch pattern followed by an identifier. Among these

three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.

Frame slot

Frame

Response

Inter-

frame

space

Response

space

Header

Synch Protected

identifier

Data 1 Data 2 Data N Checksum

,/ Infineon

XC866

Functional Description

Data Sheet 73 V1.2, 2007-10

The break must contain a dominant value of 13 bits or more to ensure proper

synchronization of slave nodes.

In the LIN communication, a slave task is required to be synchronized at the beginning

of the protected identifier field of frame. For this purpose, every frame starts with a

sequence consisting of a break field followed by a synch byte field. This sequence is

unique and provides enough information for any slave task to detect the beginning of a

new frame and be synchronized at the start of the identifier field.

Upon entering LIN communication, a connection is established and the transfer speed

(baud rate) of the serial communication partner (host) is automatically synchronized in

the following steps:

STEP 1: Initialize interface for reception and timer for baud rate measurement

STEP 2: Wait for an incoming LIN frame from host

STEP 3: Synchronize the baud rate to the host

STEP 4: Enter for Master Request Frame or for Slave Response Frame

Note: Re-synchronization and setup of baud rate are always done for every Master

Request Header or Slave Response Header LIN frame.

,/ Infineon

XC866

Functional Description

Data Sheet 74 V1.2, 2007-10

3.14 High-Speed Synchronous Serial Interface

The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and

half-duplex synchronous communication. The serial clock signal can be generated by

the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be

received from an external master (slave mode). Data width, shift direction, clock polarity

and phase are programmable. This allows communication with SPI-compatible devices

or devices using other synchronous serial interfaces.

Features:

• Master and slave mode operation

– Full-duplex or half-duplex operation

• Transmit and receive buffered

• Flexible data format

– Programmable number of data bits: 2 to 8 bits

– Programmable shift direction: LSB or MSB shift first

– Programmable clock polarity: idle low or high state for the shift clock

– Programmable clock/data phase: data shift with leading or trailing edge of the shift

clock

• Variable baud rate

• Compatible with Serial Peripheral Interface (SPI)

• Interrupt generation

– On a transmitter empty condition

– On a receiver full condition

– On an error condition (receive, phase, baud rate, transmit error)

0/ Infineon

XC866

Functional Description

Data Sheet 75 V1.2, 2007-10

Data is transmitted or received on lines TXD and RXD, which are normally connected to

the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave

Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input

via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin

SCLK. Transmission and reception of data are double-buffered.

Figure 31 shows the block diagram of the SSC.

Figure 31 SSC Block Diagram

PCLK SS_CLK

RIR

TIR

EIR

Receive Int. Request

Transmit Int. Request

Error Int. Request

ControlStatus

TXD(Mas ter)

RXD(Slave)

Shift

Clock

MS_CLK

RXD(Master)

TXD(Slave)

Internal Bus

Baud-rate

Generator

Clock

Control

SSC Control Block

Control

16-Bit Shift

Transmit Buffer

Receive Buffer

n/ Infineon

XC866

Functional Description

Data Sheet 76 V1.2, 2007-10

3.15 Timer 0 and Timer 1

Timers 0 and 1 are count-up timers which are incremented every machine cycle, or in

terms of the input clock, every 2 PCLK cycles. They are fully compatible and can be

configured in four different operating modes for use in a variety of applications, see

Table 28. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their

functions are specialized.

Table 28 Timer 0 and Timer 1 Modes

Mode Operation

0 13-bit timer

The timer is essentially an 8-bit counter with a divide-by-32 prescaler.

This mode is included solely for compatibility with Intel 8048 devices.

1 16-bit timer

The timer registers, TLx and THx, are concatenated to form a 16-bit

counter.

2 8-bit timer with auto-reload

The timer register TLx is reloaded with a user-defined 8-bit value in THx

upon overflow.

3 Timer 0 operates as two 8-bit timers

The timer registers, TL0 and TH0, operate as two separate 8-bit counters.

Timer 1 is halted and retains its count even if enabled.

n/ Infineon

XC866

Functional Description

Data Sheet 77 V1.2, 2007-10

3.16 Timer 2

Timer 2 is a 16-bit general purpose timer (THL2) that has two modes of operation, a

16-bit auto-reload mode and a 16-bit one channel capture mode. If the prescalar is

disabled, Timer 2 counts with an input clock of PCLK/12. Timer 2 continues counting as

long as it is enabled.

Table 29 Timer 2 Modes

Mode Description

Auto-reload Up/Down Count Disabled

• Count up only

• Start counting from 16-bit reload value, overflow at FFFFH

• Reload event configurable for trigger by overflow condition only, or by

negative/positive edge at input pin T2EX as well

• Programmble reload value in register RC2

• Interrupt is generated with reload event

Up/Down Count Enabled

• Count up or down, direction determined by level at input pin T2EX

• No interrupt is generated

• Count up

– Start counting from 16-bit reload value, overflow at FFFFH

– Reload event triggered by overflow condition

– Programmble reload value in register RC2

• Count down

– Start counting from FFFFH, underflow at value defined in register

RC2

– Reload event triggered by underflow condition

– Reload value fixed at FFFFH

Channel

capture

• Count up only

• Start counting from 0000H, overflow at FFFFH

• Reload event triggered by overflow condition

• Reload value fixed at 0000H

• Capture event triggered by falling/rising edge at pin T2EX

• Captured timer value stored in register RC2

• Interrupt is generated with reload or capture event

,/ Infineon

XC866

Functional Description

Data Sheet 78 V1.2, 2007-10

3.17 Capture/Compare Unit 6

The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which

can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor

control. The CCU6 also supports special control modes for block commutation and

multi-phase machines.

The timer T12 can function in capture and/or compare mode for its three channels. The

timer T13 can work in compare mode only.

The multi-channel control unit generates output patterns, which can be modulated by

T12 and/or T13. The modulation sources can be selected and combined for the signal

modulation.

Timer T12 Features:

• Three capture/compare channels, each channel can be used either as a capture or as

a compare channel

• Supports generation of a three-phase PWM (six outputs, individual signals for

highside and lowside switches)

• 16-bit resolution, maximum count frequency = peripheral clock frequency

• Dead-time control for each channel to avoid short-circuits in the power stage

• Concurrent update of the required T12/13 registers

• Generation of center-aligned and edge-aligned PWM

• Supports single-shot mode

• Supports many interrupt request sources

• Hysteresis-like control mode

Timer T13 Features:

• One independent compare channel with one output

• 16-bit resolution, maximum count frequency = peripheral clock frequency

• Can be synchronized to T12

• Interrupt generation at period-match and compare-match

• Supports single-shot mode

Additional Features:

• Implements block commutation for Brushless DC-drives

• Position detection via Hall-sensor pattern

• Automatic rotational speed measurement for block commutation

• Integrated error handling

• Fast emergency stop without CPU load via external signal (CTRAP)

• Control modes for multi-channel AC-drives

• Output levels can be selected and adapted to the power stage

0/ Infineon

XC866

Functional Description

Data Sheet 79 V1.2, 2007-10

The block diagram of the CCU6 module is shown in Figure 32.

Figure 32 CCU6 Block Diagram

channel 0

channel 1

channel 2

T12

dead-

time

control

input / output control

CC62

COUT62

CC61

COUT61

CC60

COUT60

COUT63

CTRAP

channel 3T13

CCPOS0

2221

start

compare

capture

multi-

channel

control

address

decoder

clock

control

interrupt

control

trap

control

compare

compar e

tr ap input

port control

CCPOS1

CCPOS2

output select

Hall input

module kernel

CCU6_block_diagram

T13HR

T12HR

,/ Infineon

XC866

Functional Description

Data Sheet 80 V1.2, 2007-10

3.18 Analog-to-Digital Converter

The XC866 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with

eight multiplexed analog input channels. The ADC uses a successive approximation

technique to convert the analog voltage levels from up to eight different sources. The

analog input channels of the ADC are available at Port 2.

Features:

• Successive approximation

• 8-bit or 10-bit resolution

(TUE of ±1 LSB and ±2 LSB, respectively)

• Eight analog channels

• Four independent result registers

• Result data protection for slow CPU access

(wait-for-read mode)

• Single conversion mode

• Autoscan functionality

• Limit checking for conversion results

• Data reduction filter

(accumulation of up to 2 conversion results)

• Two independent conversion request sources with programmable priority

• Selectable conversion request trigger

• Flexible interrupt generation with configurable service nodes

• Programmable sample time

• Programmable clock divider

• Cancel/restart feature for running conversions

• Integrated sample and hold circuitry

• Compensation of offset errors

• Low power modes

Inflneon

XC866

Functional Description

Data Sheet 81 V1.2, 2007-10

3.18.1 ADC Clocking Scheme

A common module clock fADC generates the various clock signals used by the analog

and digital parts of the ADC module:

•f

ADCA is input clock for the analog part.

•f

ADCI is internal clock for the analog part (defines the time base for conversion length

and the sample time). This clock is generated internally in the analog part, based on

the input clock fADCA to generate a correct duty cycle for the analog components.

•f

ADCD is input clock for the digital part.

The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz.

Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI

does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register

GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of

the ADC is not required.

Figure 33 ADC Clocking Scheme

analog

components

ADCI

ADC

= f

PCLK

MUX

arbi ter

regi sters

interrupts

analog part

digital part

ADCD

ADCA

clock prescaler

CTC

≤

Condition: f

ADCI

10 MHz, where t

ADCI =

ADCI

Inflneon

XC866

Functional Description

Data Sheet 82 V1.2, 2007-10

For module clock fADC = 26.7 MHz, the analog clock fADCI frequency can be selected as

shown in Table 30.

As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00B when fADC is

26.7 MHz. During slow-down mode where fADC may be reduced to 13.3 MHz, 6.7 MHz

etc., CTC can be set to 00B as long as the divided analog clock fADCI does not exceed

10 MHz. However, it is important to note that the conversion error could increase due to

loss of charges on the capacitors, if fADC becomes too low during slow-down mode.

3.18.2 ADC Conversion Sequence

The analog-to-digital conversion procedure consists of the following phases:

• Synchronization phase (tSYN)

• Sample phase (tS)

• Conversion phase

• Write result phase (tWR)

Figure 34 ADC Conversion Timing

Table 30 fADCI Frequency Selection

Module Clock fADC CTC Prescaling Ratio Analog Clock fADCI

26.7 MHz 00B÷ 2 13.3 MHz (N.A)

01B÷3 8.9MHz

10B÷4 6.7MHz

11B (default) ÷ 32 833.3 kHz

CONV

SAMPLE Bit

BUSY Bit

Conversion PhaseSample Phase

Write Result Phase

conversion start

trigger

Source

interrupt

Result

interrupt

SYN

Channel

interrupt

ADCI

,/ Infineon

XC866

Functional Description

Data Sheet 83 V1.2, 2007-10

3.19 On-Chip Debug Support

The On-Chip Debug Support (OCDS) provides the basic functionality required for the

software development and debugging of XC800-based systems.

The OCDS design is based on these principles:

• use the built-in debug functionality of the XC800 Core

• add a minimum of hardware overhead

• provide support for most of the operations by a Monitor Program

• use standard interfaces to communicate with the Host (a Debugger)

Features:

• Set breakpoints on instruction address and within a specified address range

• Set breakpoints on internal RAM address

• Support unlimited software breakpoints in Flash/RAM code region

• Process external breaks

• Step through the program code

The OCDS functional blocks are shown in Figure 35. The Monitor Mode Control (MMC)

block at the center of OCDS system brings together control signals and supports the

overall functionality. The MMC communicates with the XC800 Core, primarily via the

Debug Interface, and also receives reset and clock signals. After processing memory

address and control signals from the core, the MMC provides proper access to the

dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for

work-data and Monitor-stack). The OCDS system is accessed through the JTAG1),

which is an interface dedicated exclusively for testing and debugging activities and is not

normally used in an application. The dedicated MBC pin is used for external

configuration and debugging control.

Note: All the debug functionality described here can normally be used only after XC866

has been started in OCDS mode.

1) The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary).

User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.

XC866

Functional Description

Data Sheet 84 V1.2, 2007-10

Figure 35 OCDS Block Diagram

3.19.1 JTAG ID Register

This is a read-only register located inside the JTAG module, and is used to recognize the

device(s) connected to the JTAG interface. Its content is shifted out when

INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is

also true immediately after reset.

The JTAG ID register contents for the XC866 devices are given in Table 31.

Table 31 JTAG ID Summary

Device Type Device Name JTAG ID

Flash XC866L-4FR 1010 0083H

XC866-4FR 100F 5083H

XC866L-2FR 1010 2083H

XC866-2FR 1010 1083H

XC866L-1FR 1013 8083H

XC866-1FR 1013 8083H

JTAG Module

Monitor &

Bootstrap loader

Control line

JTAG

Memory

Control

Unit

User

Program

Memory

XC800

PROG

& IRAM

Addresses

Debug

Interface

Reset Clock

TMS

TCK

TDI

TDO

TCK

TDI

TDO

Control

Memory

Control

Primary

Debug

Interface

System

Control

Unit

Boot/

Monitor

ROM

Monitor

RAM

User

Internal

RAM

Reset

Clock

PROG

Data

Monitor Mode Control

MBC

- parts of

OCDS

WDT

Suspend

OCDS_XC800-Block_Diagram-UM-v0.2

n/ Infineon

XC866

Functional Description

Data Sheet 85 V1.2, 2007-10

3.20 Identification Register

The XC866 identity register is located at Page 1 of address B3H.

ROM XC866L-4RR 1013 9083H

XC866-4RR 1013 9083H

XC866L-2RR 1013 9083H

XC866-2RR 1013 9083H

Identity Register Reset Value: 0000 0010B

76543210

PRODID VERID

Field Bits Type Description

VERID [2:0] r Version ID

010B

PRODID [7:3] r Product ID

00000B

Table 31 JTAG ID Summary

,/ Infineon

XC866

Electrical Parameters

Data Sheet 86 V1.2, 2007-10

4 Electrical Parameters

Chapter 4 provides the characteristics of the electrical parameters which are

implementation-specific for the XC866.

Note: The electrical parameters are valid for the XC866-4FR and XC866-2FR. The

electrical parameters for the ROM variants and XC866-1FR are preliminary,

differences from XC866-4FR and XC866-2FR are stated explicitly.

4.1 General Parameters

The general parameters are described here to aid the users in interpreting the

parameters mainly in Section 4.2 and Section 4.3.

4.1.1 Parameter Interpretation

The parameters listed in this section represent partly the characteristics of the XC866

and partly its requirements on the system. To aid interpreting the parameters easily

when evaluating them for a design, they are indicated by the abbreviations in the

“Symbol” column:

•CC

These parameters indicate Controller Characteristics, which are distinctive features of

the XC866 and must be regarded for a system design.

•SR

These parameters indicate System Requirements, which must be provided by the

microcontroller system in which the XC866 is designed in.

n/ Infineon

XC866

Electrical Parameters

Data Sheet 87 V1.2, 2007-10

4.1.2 Absolute Maximum Rating

Maximum ratings are the extreme limits to which the XC866 can be subjected to without

permanent damage.

Table 32 Absolute Maximum Rating Parameters

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions (VIN >V

DDP or VIN <V

SS)

the voltage on VDDP pin with respect to ground (VSS) must not exceed the values

defined by the absolute maximum ratings.

Parameter Symbol Limit Values Unit Notes

min. max.

Ambient temperature TA-40 125 °C under bias

Storage temperature TST -65 150 °C

Junction temperature TJ-40 150 °C under bias

Voltage on power supply pin with

respect to VSS

VDDP -0.5 6 V

Voltage on core supply pin with

respect to VSS

VDDC -0.5 3.25 V

Voltage on any pin with respect

to VSS

VIN -0.5 VDDP +

0.5 or

max. 6

V Whatever is

lower

Input current on any pin during

overload condition

IIN -10 10 mA

Absolute sum of all input currents

during overload condition

Σ|IIN|– 50 mA

Inflneon nay”

XC866

Electrical Parameters

Data Sheet 88 V1.2, 2007-10

4.1.3 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation of the XC866. All parameters mentioned in the following table refer to these

operating conditions, unless otherwise noted.

Table 33 Operating Condition Parameters

Parameter Symbol Limit Values Unit Notes/

Conditions

min. max.

Digital power supply voltage VDDP 4.5 5.5 V 5V Device

Digital power supply voltage VDDP 3.0 3.6 V 3.3V Device

Digital ground voltage VSS 0V

Digital core supply voltage VDDC 2.3 2.7 V

System Clock Frequency1)

1) fSYS is the PLL output clock. During normal operating mode, CPU clock is fSYS / 3. Please refer to Figure 25

for detailed description.

fSYS 74 86 MHz

Ambient temperature TA-40 85 °C SAF-XC866...

-40 125 °C SAK-XC866...

Inflneon esis‘) esis“

XC866

Electrical Parameters

Data Sheet 89 V1.2, 2007-10

4.2 DC Parameters

4.2.1 Input/Output Characteristics

Table 34 Input/Output Characteristics (Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Conditions

Remarks

min. max.

VDDP = 5V Range

Output low voltage VOL CC – 1.0 V IOL =15mA

–0.4V

IOL =5mA

Output high voltage VOH CC VDDP -

1.0

–VIOH =-15mA

VDDP -

0.4

–VIOH =-5mA

Input low voltage on

port pins

(all except P0.0 & P0.1)

VILP SR – 0.3 ×

VDDP

V CMOS Mode

Input low voltage on

P0.0 & P0.1

VILP0 SR -0.2 0.3 ×

VDDP

V CMOS Mode

Input low voltage on

RESET pin

VILR SR – 0.3 ×

VDDP

V CMOS Mode

Input low voltage on

TMS pin

VILT SR – 0.3 ×

VDDP

V CMOS Mode

Input high voltage on

port pins

(all except P0.0 & P0.1)

VIHP SR 0.7 ×

VDDP

–VCMOS Mode

Input high voltage on

P0.0 & P0.1

VIHP0 SR 0.7 ×

VDDP

VDDP V CMOS Mode

Input high voltage on

RESET pin

VIHR SR 0.7 ×

VDDP

–VCMOS Mode

Input high voltage on

TMS pin

VIHT SR 0.75 ×

VDDP

–VCMOS Mode

Input Hysteresis1) on

Port pins

HYS CC 0.08 ×

VDDP

–VCMOS Mode

Input Hysteresis1) on

XTAL1

HYSXCC 0.07 ×

VDDC

–V

Inflneon 3D 4’

XC866

Electrical Parameters

Data Sheet 90 V1.2, 2007-10

Input low voltage at

XTAL1

VILX SR VSS -

0.5

0.3 ×

VDDC

Input high voltage at

XTAL1

VIHX SR 0.7 ×

VDDC

+0.5

Pull-up current IPU SR – -10 µA VIH,min

-150 – µA VIL,max

Pull-down current IPD SR – 10 µA VIL,max

150 – µA VIH,min

Input leakage current2) IOZ1 CC -1 1 µA 0 < VIN < VDDP,

TA≤125°C , XC866-4FR

and XC866-2FR

-2.5 1 µA 0 < VIN < VDDP,

TA≤125°C, XC866-1FR

and ROM device

Input current at XTAL1 IILX CC -10 10 µA

Overload current on any

IOV SR -5 5 mA

Absolute sum of

overload currents

Σ|IOV|

–25mA

Voltage on any pin

during VDDP power off

VPO SR – 0.3 V 4)

Maximum current per

pin (excluding VDDP and

VSS)

IM SR – 15 mA

Maximum current for all

pins (excluding VDDP

and VSS)

Σ|IM|

–60mA

Maximum current into

VDDP

IMVDDP

–80mA

Maximum current out of

VSS

IMVSS

–80mA

Table 34 Input/Output Characteristics (Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Conditions

Remarks

min. max.

Inflneon esis“ esis“

XC866

Electrical Parameters

Data Sheet 91 V1.2, 2007-10

VDDP = 3.3V Range

Output low voltage VOL CC – 1.0 V IOL =8mA

–0.4V

IOL =2.5mA

Output high voltage VOH CC VDDP -

1.0

–VIOH =-8mA

VDDP -

0.4

–VIOH =-2.5mA

Input low voltage on

port pins

(all except P0.0 & P0.1)

VILP SR – 0.3 ×

VDDP

V CMOS Mode

Input low voltage on

P0.0 & P0.1

VILP0 SR -0.2 0.3 ×

VDDP

V CMOS Mode

Input low voltage on

RESET pin

VILR SR – 0.3 ×

VDDP

V CMOS Mode

Input low voltage on

TMS pin

VILT SR – 0.3 ×

VDDP

V CMOS Mode

Input high voltage on

port pins

(all except P0.0 & P0.1)

VIHP SR 0.7 ×

VDDP

–VCMOS Mode

Input high voltage on

P0.0 & P0.1

VIHP0 SR 0.7 ×

VDDP

VDDP V CMOS Mode

Input high voltage on

RESET pin

VIHR SR 0.7 ×

VDDP

–VCMOS Mode

Input high voltage on

TMS pin

VIHT SR 0.75 ×

VDDP

–VCMOS Mode

Input Hysteresis1) on

Port pins

HYS CC 0.03 ×

VDDP

–VCMOS Mode

Input Hysteresis1) on

XTAL1

HYSXCC 0.07 ×

VDDC

–V

Input low voltage at

XTAL1

VILX SR VSS -

0.5

0.3 ×

VDDC

Input high voltage at

XTAL1

VIHX SR 0.7 ×

VDDC

+0.5

Table 34 Input/Output Characteristics (Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Conditions

Remarks

min. max.

Inflneon 2) 3) 4) An adm RESET

XC866

Electrical Parameters

Data Sheet 92 V1.2, 2007-10

Pull-up current IPU SR – -5 µA VIH,min

-50 – µA VIL,max

Pull-down current IPD SR – 5 µA VIL,max

50 – µA VIH,min

Input leakage current2) IOZ1 CC -1 1 µA 0 < VIN < VDDP,

TA≤125°C , XC866-4FR

and XC866-2FR

-2.5 1 µA 0 < VIN < VDDP,

TA≤125°C, XC866-1FR

and ROM device

Input current at XTAL1 IILX CC - 10 10 µA

Overload current on any

IOV SR -5 5 mA

Absolute sum of

overload currents

Σ|IOV|

–25mA

Voltage on any pin

during VDDP power off

VPO SR – 0.3 V 4)

Maximum current per

pin (excluding VDDP and

VSS)

IM SR – 15 mA

Maximum current for all

pins (excluding VDDP

and VSS)

Σ|IM|

–60mA

Maximum current into

VDDP

IMVDDP

–80mA

Maximum current out of

VSS

IMVSS

–80mA

1) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta

stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching

due to external system noise.

2) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and

RESET pin have internal pull devices and are not included in the input leakage current characteristic.

3) Not subjected to production test, verified by design/characterization.

Table 34 Input/Output Characteristics (Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Conditions

Remarks

min. max.

,/ Infineon

XC866

Electrical Parameters

Data Sheet 93 V1.2, 2007-10

4) Not subjected to production test, verified by design/characterization. However, for applications with strict low

power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin

when VDDP is powered off.

Inflneon 3) 2)“

XC866

Electrical Parameters

Data Sheet 94 V1.2, 2007-10

4.2.2 Supply Threshold Characteristics

Figure 36 Supply Threshold Parameters

Table 35 Supply Threshold Parameters (Operating Conditions apply)

Parameters Symbol Limit Values Unit Remarks

min. typ. max.

VDDC prewarning voltage1)

1) Detection is disabled in power-down mode.

VDDCPW CC 2.2 2.3 2.4 V

VDDC brownout voltage in

active mode1)

VDDCBO CC 2.0 2.1 2.2 V XC866-4FR,

XC866-2FR

2.0 2.1 2.3 V XC866-1FR,

ROM device

RAM data retention voltage VDDCRDR CC 0.9 1.0 1.1 V

VDDC brownout voltage in

power-down mode2)

2) Detection is enabled in both active and power-down mode.

VDDCBOPD CC 1.3 1.5 1.7 V

VDDP prewarning voltage3)

3) Detection is enabled for external power supply of 5.0V.

Detection must be disabled for external power supply of 3.3V.

VDDPPW CC 3.4 4.0 4.6 V

Power-on reset voltage2)4)

4) The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage.

VDDCPOR CC 1.3 1.5 1.7 V

VDDP

VDDC

DDPPW

DDCPOR

DDCPW

DDCBO

DDCBOPD

5.0V

2.5V

DDCRDR

Inflneon 1) 2’ nz’ nz’ nz’ nz’ 2m

XC866

Electrical Parameters

Data Sheet 95 V1.2, 2007-10

4.2.3 ADC Characteristics

The values in the table below are given for an analog power supply between 4.5 V to

5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case,

the analog parameters may show a reduced performance. All ground pins (VSS) must be

externally connected to one single star point in the system. The voltage difference

between the ground pins must not exceed 200mV.

Table 36 ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)

Parameter Symbol Limit Values Unit Test Conditions/

Remarks

min. typ . max.

Analog reference

voltage

VAREF

VAGND

+ 1

VDDP VDDP

+ 0.05

Analog reference

ground

VAGND

VSS

- 0.05

VSS VAREF

- 1

Analog input

voltage range

VAIN SR VAGND –VAREF V

ADC clocks fADC – 20 40 MHz module clock

fADCI – – 10 MHz internal analog clock

See Figure 33

Sample time tSCC (2 + INPCR0.STC) ×

tADCI

µs

Conversion time tCCC See Section 4.2.3.1 µs

Total unadjusted

error

TUE1)CC – – ±1 LSB 8-bit conversion.2)

––±2 LSB 10-bit conversion.

Differential

Nonlinearity

DNL CC – ±1 – LSB 10-bit conversion2)

Integral

Nonlinearity

INL CC – ±1 – LSB 10-bit conversion2)

Offset OFF CC – ±1 – LSB 10-bit conversion2)

Gain GAIN CC – ±1 – LSB 10-bit conversion2)

Switched

capacitance at the

reference voltage

input

CAREFSW

–1020pF

2)3)

Inflneon 2W 2D 2D

XC866

Electrical Parameters

Data Sheet 96 V1.2, 2007-10

Switched

capacitance at the

analog voltage

inputs

CAINSW

–57pF

2)4)

Input resistance of

the reference input

RAREFCC – 1 2 kΩ2)

Input resistance of

the selected analog

channel

RAIN CC – 1 1.5 kΩ2)

1) TUE is tested at VAREF =5.0V, VAGND =0V , VDDP =5.0V.

2) Not subject to production test, verified by design/characterization.

3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage

at once. Instead of this, smaller capacitances are successively switched to the reference voltage.

4) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to

the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2.

Table 36 ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)

Parameter Symbol Limit Values Unit Test Conditions/

Remarks

min. typ . max.

/ infineon x 7 < 7="" \="" %="" r="" agndx="" ,="">

XC866

Electrical Parameters

Data Sheet 97 V1.2, 2007-10

Figure 37 ADC Input Circuits

4.2.3.1 ADC Conversion Timing

Conversion time, tC=t

ADC ×( 1 + r ×(3 + n + STC) ) , where

r = CTC + 2 for CTC = 00B, 01B or 10B,

r = 32 for CTC = 11B,

CTC = Conversion Time Control (GLOBCTR.CTC),

STC = Sample Time Control (INPCR0.STC),

n = 8 or 10 (for 8-bit and 10-bit conversion respectively),

tADC =1/f

ADC

AGNDx

EXT

Analog Input Circuitry

AIN

EXT

ANx

AINSW

AIN, On

AGNDx

Reference Voltage Input Circuitry

AREFSW

AREF, On

AREFx

AREF

Inflneon lypﬂ) x?’ :n nun duck ta RESET RESET ktoaHp

XC866

Electrical Parameters

Data Sheet 98 V1.2, 2007-10

4.2.4 Power Supply Current

Table 37 Power Supply Current Parameters (Operating Conditions apply;

VDDP = 5V range )

Parameter Symbol Limit Values Unit Test Condition

Remarks

typ.1)

1) The typical IDDP values are periodically measured at TA=+25°C and VDDP =5.0V.

max.2)

2) The maximum IDDP values are measured under worst case conditions (TA= + 125 °C and VDDP =5.5V).

VDDP = 5V Range

Active Mode IDDP 22.6 24.5 mA 3)

3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz(set by

on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010B), RESET =VDDP, no load on ports.

Idle Mode IDDP 17.2 19.7 mA XC866-4FR,

XC866-2FR 4)

4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals

enabled and running at 26.7 MHz, RESET =VDDP , no load on ports.

12.5 14 mA XC866-1FR,

ROM device4)

Active Mode with slow-down

enabled

IDDP 7.2 8.2 mA XC866-4FR,

XC866-2FR 5)

5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running

at 833 KHz by setting CLKREL in CMCON to 0101B, RESET =VDDP, no load on ports.

5.6 7.5 mA XC866-1FR,

ROM device5)

Idle Mode with slow-down

enabled

IDDP 7.1 8 mA XC866-4FR,

XC866-2FR 6)

6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input

clock to all peripherals enabled and running at 833 KHz by setting CLKREL in CMCON to 0101B,

RESET =VDDP, no load on ports.

5.1 7.2 mA XC866-1FR,

ROM device6)

Inflneon 1) .3 h RESET

XC866

Electrical Parameters

Data Sheet 99 V1.2, 2007-10

Table 38 Power Down Current (Operating Conditions apply; VDDP = 5V range )

Parameter Symbol Limit Values Unit Test Condition

Remarks

typ.1)

1) The typical IPDP values are measured at VDDP =5.0V.

max.2)

2) The maximum IPDP values are measured at VDDP =5.5V.

VDDP = 5V Range

Power-Down Mode3)

3) IPDP (power-down mode) has a maximum value of 200 µA at TA= + 125 °C.

IPDP 110µATA=+25°C.4)

4) IPDP (power-down mode) is measured with: RESET =VDDP, VAGND=VSS, RXD/INT0 = VDDP; rest of the ports

are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating

inputs.

-30µATA=+85°C, XC866-

4FR, XC866-2FR 4)5)

5) Not subject to production test, verified by design/characterization.

-35µATA=+85°C, XC866-

1FR, ROM device4)5)

Inflneon 1 2 .yp‘ ) ‘ x, J :n k ‘0 5H 9 v RESET CPU do RESET RESET aw duck to RESET

XC866

Electrical Parameters

Data Sheet 100 V1.2, 2007-10

Table 39 Power Supply Current Parameters (Operating Conditions apply;

VDDP = 3.3V range)

Parameter Symbol Limit Values Unit Test Condition

Remarks

typ.1)

1) The typical IDDP values are periodically measured at TA=+25°C and VDDP =3.3V.

max.2)

2) The maximum IDDP values are measured under worst case conditions (TA= + 125 °C and VDDP =3.6V).

VDDP = 3.3V Range

Active Mode IDDP 21.5 23.3 mA 3)

3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz(set by

on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010B), RESET =VDDP, no load on ports.

Idle Mode IDDP 16.4 18.9 mA XC866-4FR,

XC866-2FR 4)

4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals

enabled and running at 26.7 MHz, RESET =VDDP, no load on ports.

11.2 13.5 mA XC866-1FR,

ROM device 4)

Active Mode with slow-down

enabled

IDDP 6.8 8 mA XC866-4FR,

XC866-2FR 5)

5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals

running at 833 KHz by setting CLKREL in CMCON to 0101B, RESET =VDDP, no load on ports.

5.4 7.3 mA XC866-1FR,

ROM device 5)

Idle Mode with slow-down

enabled

IDDP 6.8 7.8 mA XC866-4FR,

XC866-2FR 6)

6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input

clock to all peripherals enable and running at 833 KHz by setting CLKREL in CMCON to 0101B,,

RESET =VDDP, no load on ports.

4.9 6.9 mA XC866-1FR,

ROM device 6)

Inflneon 1) 2 RESET

XC866

Electrical Parameters

Data Sheet 101 V1.2, 2007-10

Table 40 Power Down Current (Operating Conditions apply; VDDP = 3.3V

range )

Parameter Symbol Limit Values Unit Test Condition

Remarks

typ.1)

1) The typical IPDP values are measured at VDDP =3.3V.

max.2)

2) The maximum IPDP values are measured at VDDP =3.6V.

VDDP = 3.3V Range

Power-Down Mode3)

3) IPDP (power-down mode) has a maximum value of 200 µA at TA= + 125 °C.

IPDP 110µATA=+25°C.4)

4) IPDP (power-down mode) is measured with: RESET =VDDP, VAGND=VSS, RXD/INT0= VDDP; rest of the ports

are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating

inputs.

-30µATA=+85°C, XC866-

4FR, XC866-2FR4)5)

5) Not subject to production test, verified by design/characterization.

-35µATA=+85°C, XC866-

1FR, ROM device4)5)

0/ Infineon

XC866

Electrical Parameters

Data Sheet 102 V1.2, 2007-10

4.3 AC Parameters

4.3.1 Testing Waveforms

The testing waveforms for rise/fall time, output delay and output high impedance are

shown in Figure 38, Figure 39 and Figure 40.

Figure 38 Rise/Fall Time Parameters

Figure 39 Testing Waveform, Output Delay

Figure 40 Testing Waveform, Output High Impedance

10%

90%

10%

90%

DDP

DDE

/ 2 Te st P o in ts V

DDE

/ 2

DDP

Load

+ 0.1 V V

- 0.1 V

Timing

Reference

Points

Load

- 0.1 V V

- 0.1 V

Inflneon

XC866

Electrical Parameters

Data Sheet 103 V1.2, 2007-10

4.3.2 Output Rise/Fall Times

Figure 41 Rise/Fall Times Parameters

Table 41 Output Rise/Fall Times Parameters (Operating Conditions apply)

Parameter Symbol Limit

Values

Unit Test Conditions

min. max.

VDDP = 5V Range

Rise/fall times 1) 2)

1) Rise/Fall time measurements are taken with 10% - 90% of the pad supply.

2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.

tR, tF– 10 ns 20 pF. 3)

3) Additional rise/fall time valid for CL= 20pF - 100pF @ 0.125 ns/pF.

VDDP = 3.3V Range

Rise/fall times 1) 2) tR, tF– 10 ns 20 pF. 4)

4) Additional rise/fall time valid for CL= 20pF - 100pF @ 0.225 ns/pF.

10%

90%

10%

90%

DDP

Inflneon RESET

XC866

Electrical Parameters

Data Sheet 104 V1.2, 2007-10

4.3.3 Power-on Reset and PLL Timing

Table 42 Power-On Reset and PLL Timing (Operating Conditions apply)

Figure 42 Power-on Reset Timing

Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

Pad operating voltage VPAD CC 2.3 – – V

On-Chip Oscillator

start-up time

tOSCST

––500ns

Flash initialization time tFINIT CC – 160 – µs

RESET hold time1)

1) RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5V).

tRST SR – 500 – µs VDDP rise time

(10% – 90%) ≤ 500µs

PLL lock-in in time tLOCK CC – – 200 µs

PLL accumulated jitter DP––0.7ns

2) PLL lock at 80 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 40 and P = 1.

VDDP

Pads

VDDC

PAD

OSC

OSCST

PLL

Reset Initialization Ready to ReadFlash State

PLL unlock PLL lock

2) 3)

LOCK

FINIT

1)Pad state undefined 2)ENPS control 3)As Programmed

I)until EVR is stable II)until PLL is locked III) until Flash go

to Re ady-to-Read

IV) CPU reset is released; Boot

ROM software begin execution

RESET

RST

n/ Infineon

XC866

Electrical Parameters

Data Sheet 105 V1.2, 2007-10

4.3.4 On-Chip Oscillator Characteristics

Table 43 On-chip Oscillator Characteristics (Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

Nominal frequency fNOM CC 9.75 10 10.25 MHz under nominal

conditions1) after

IFX-backend trimming

1) Nominal condition: VDDC =2.5V, TA=+25°C.

Long term frequency

deviation2)

2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.

∆fLT CC -5.0 – 5.0 % with respect to fNOM, over

lifetime and temperature (−

10°C to 125°C), for one

device after trimming

-6.0 – 0 % with respect to fNOM, over

lifetime and temperature (−

40°C to -10°C), for one

device after trimming

Short term frequency

deviation

∆fST CC -1.0 – 1.0 % with respect to fNOM, within

one LIN message (<10 ms

.... 100 ms)

0/ Infineon

XC866

Electrical Parameters

Data Sheet 106 V1.2, 2007-10

4.3.5 JTAG Timing

Table 44 TCK Clock Timing (Operating Conditions apply; CL= 50 pF)

Figure 43 TCK Clock Timing

Parameter Symbol Limits Unit

min max

TCK clock period tTCK SR 50 −ns

TCK high time t1 SR 20 −ns

TCK low time t2 SR 20 −ns

TCK clock rise time t3 SR −4 ns

TCK clock fall time t4 SR −4 ns

TCK

0.9 V

DDP

0.1 V

DDP

TCK

0.5 V

DDP

Inflneon “KKK

XC866

Electrical Parameters

Data Sheet 107 V1.2, 2007-10

Table 45 JTAG Timing (Operating Conditions apply; CL=50 pF)

Figure 44 JTAG Timing

Parameter Symbol Limits Unit

min max

TMS setup to TCK t1 SR 8.0 −ns

TMS hold to TCK t2 SR 5.0 −ns

TDI setup to TCK t1 SR 11.0 −ns

TDI hold to TCK t2 SR 6.0 −ns

TDO valid output from TCK t3 CC −23 ns

TDO high impedance to valid output from TCK t4 CC −26 ns

TDO valid output to high impedance from TCK t5 CC −18 ns

TMS

TDI

TCK

TDO

0/ Infineon

XC866

Electrical Parameters

Data Sheet 108 V1.2, 2007-10

4.3.6 SSC Master Mode Timing

Table 46 SSC Master Mode Timing (Operating Conditions apply; CL= 50 pF)

Figure 45 SSC Master Mode Timing

Parameter Symbol Limit Values Unit

min. max.

SCLK clock period t0CC 2*TSSC 1)

1) TSSCmin =T

CPU =1/f

CPU. When fCPU = 26.7MHz, t0 = 74.9ns. TCPU is the CPU clock period.

–ns

MTSR delay from SCLK t1CC 0 8 ns

MRST setup to SCLK t2SR 22 – ns

MRST hold from SCLK t3SR 0 – ns

SSC_Tmg1

SCLK

MTSR

MRST

Data

valid

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

Inflneon

XC866

Package and Reliability

Data Sheet 109 V1.2, 2007-10

5 Package and Reliability

5.1 Package Parameters (PG-TSSOP-38)

Table 47 provides the thermal characteristics of the package.

Table 47 Thermal Characteristics of the Package

Parameter Symbol Limit Values Unit Notes

Min. Max.

Thermal resistance junction

case1)

1) The thermal resistances between the case and the ambient (RTCA) , the lead and the ambient (RTLA) are to

be combined with the thermal resistances between the junction and the case (RTJC), the junction and the lead

(RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient

(RTJA). The thermal resistances between the case and the ambient (RTCA), the lead and the ambient (RTLA)

depend on the external system (PCB, case) characteristics, and are under user responsibility.

The junction temperature can be calculated using the following equation: TJ=TA+R

TJA ×PD, where the RTJA

is the total thermal resistance between the junction and the ambient. This total junction ambient resistance

RTJA can be obtained from the upper four partial thermal resistances, by

a) simply adding only the two thermal resistances (junction lead and lead ambient), or

b) by taking all four resistances into account, depending on the precision needed.

RTJC CC – 15.7 K/W –

Thermal resistance junction

lead1)

RTJL CC – 39.2 K/W –

Inflneon 4

XC866

Package and Reliability

Data Sheet 110 V1.2, 2007-10

5.2 Package Outline

Figure 46 PG-TSSOP-38-4 Package Outline

n/ Infineon

XC866

Package and Reliability

Data Sheet 111 V1.2, 2007-10

5.3 Quality Declaration

Table 48 shows the characteristics of the quality parameters in the XC866.

Table 48 Quality Parameters

Parameter Symbol Limit Values Unit Notes

Min. Max.

ESD susceptibility

according to Human Body

Model (HBM)

VHBM – 2000 V Conforming to

EIA/JESD22-

A114-B

ESD susceptibility

according to Charged

Device Model (CDM) pins

VCDM – 500 V Conforming to

JESD22-C101-C

http://www.infineon.com

Published by Infineon Technologies AG

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XC8661FRAABKXUMA1

IC MCU 8BIT 4KB FLASH 38TSSOP

XC8661FRIABKXUMA1

IC MCU 8BIT 8KB FLASH 38TSSOP

XC8662FRIBEKXUMA1

IC MCU 8BIT 16KB FLASH 38TSSOP

XC8664FRABEKXUMA1

IC MCU 8BIT 16KB FLASH 38TSSOP

XC8664FRIBEKXUMA1

IC MCU 8BIT 4KB FLASH 38TSSOP

XC866L1FRAABKXUMA1

IC MCU 8BIT 8KB FLASH 38TSSOP

SAK-XC866L-2FRA BE

IC MCU 8BIT 8KB FLASH 38TSSOP

SAK-XC866L-2FRI BC

IC MCU 8BIT 8KB FLASH 38TSSOP

SAK-XC866L-2FRI BE

IC MCU 8BIT 16KB FLASH 38TSSOP

XC866L4FRABEKXUMA1