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01/14/09
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1
HEXFET
®
Power MOSFET
S
D
G
PD -
97363
IRLB3034PbF
GDS
Gate
Drain
Source
V
DSS
40V
R
DS(on)
typ.
1.4m
:
max.
1.7m
:
I
D (Silicon Limited)
343A
➀
I
D (Package Limited)
195A
Applications
l
DC Motor Drive
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
Benefits
l
Optimized for Logic Level Drive
l
Very Low R
DS(ON)
at 4.5V V
GS
l
Superior R*Q at 4.5V V
GS
l
Improved
Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
TO-220AB
IRLB3034PbF
Absolute Maximum Ratings
Symbol
Parameter
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Package Limited)
I
DM
Pulsed Drain Current
➁
P
D
@T
C
= 25°C
Maximum Power Dissipation
W
Linear Derating Factor
W/°C
V
GS
Gate-to-Source Voltage
V
dv/dt
Peak Diode Recovery
➃
V/ns
T
J
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
E
AS (Thermally limited)
Single Pulse Avalanche Energy
➂
mJ
I
AR
Avalanche Current
➁
A
E
AR
Repetitive Avalanche Energy
➁
mJ
Thermal Resistance
Symbol
Parameter
Typ.
Max.
Units
R
θ
JC
Junction-to-Case
➇
—
0.4
R
θ
CS
Case-to-Sink, Flat, Greased Surface
0.5
—
R
θ
JA
Junction-to-Ambient
—
62
See Fig. 14, 15, 22a, 22b,
A
°C
°C/W
255
375
4.6
±20
2.5
10lbf
x
in (1.1N
x
m)
-55
to + 175
300
Max.
343
➀
243
➀
1372
195
IRLB3034PbF
2
www.irf.com
S
D
G
➄
Pulse width
≤
400μs; duty cycle
≤
2%.
➅
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
➆
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
➇
R
θ
is measured at T
J
approximately 90°C
Notes:
➀
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 195A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
➁
Repetitive rating;
pulse width limited by max. junction
temperature.
➂
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.013mH
R
G
= 25
Ω
, I
AS
= 195A, V
GS
=10V. Part not recommended for use
above this value .
➃
I
SD
≤
195A, di/dt
≤
841A/μs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
40
—
—
V
Δ
V
(BR)DSS
/
Δ
T
J
Breakdown Voltage Temp. Coefficient
—
0.04
—
V/°C
—
1.4
1.7
—
1.6
2.0
V
GS(th)
Gate Threshold Voltage
1.0
—
2.5
V
I
DSS
Drain-to-Source Leakage Current
—
—
20
—
—
250
I
GSS
Gate-to-Source Forward Leakage
—
—
100
Gate-to-Source Reverse Leakage
—
—
-100
R
G(int)
Internal Gate Resistance
—
2.1
—
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
gfs
Forward Transconductance
286
—
—
S
Q
g
Total Gate Charge
—
108
162
Q
gs
Gate-to-Source Charge
—
29
—
Q
gd
Gate-to-Drain ("Miller") Charge
—
54
—
Q
sync
Total Gate Charge Sync. (Q
g
- Q
gd
)
—
54
—
t
d(on)
Turn-On Delay Time
—
65
—
t
r
Rise Time
—
827
—
t
d(off)
Turn-Off Delay Time
—
97
—
t
f
Fall Time
—
355
—
C
iss
Input Capacitance
— 10315 —
C
oss
Output Capacitance
—
1980
—
C
rss
Reverse Transfer Capacitance
—
935
—
C
oss
eff. (ER)
Effective Output Capacitance (Energy Related)
i
—
2378
—
C
oss
eff. (TR)
Effective Output Capacitance (Time Related)
h
—
2986
—
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
—
—
(Body Diode)
I
SM
Pulsed Source Current
—
—
(Body Diode)
d
V
SD
Diode Forward Voltage
—
—
1.3
V
t
rr
Reverse Recovery Time
—
39
—
T
J
= 25°C
V
R
= 34V,
—
41
—
T
J
= 125°C
I
F
= 195A
Q
rr
Reverse Recovery Charge
—
39
—
T
J
= 25°C
di/dt = 100A/μs
g
—
46
—
T
J
= 125°C
I
RRM
Reverse Recovery Current
—
1.7
—
A
T
J
= 25°C
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
V
GS
= 4.5V, I
D
= 172A
g
m
Ω
I
D
= 195A
R
G
= 2.1
Ω
V
GS
= 4.5V
g
V
DD
= 26V
I
D
= 185A, V
DS
=0V, V
GS
= 4.5V
Conditions
V
DS
= 10V, I
D
= 195A
I
D
= 185A
R
DS(on)
Static Drain-to-Source On-Resistance
pF
A
343
c
1372
nC
μA
nA
nC
ns
V
DS
= V
GS
, I
D
= 250μA
V
DS
= 40V, V
GS
= 0V
V
DS
= 40V, V
GS
= 0V, T
J
= 125—C
ns
V
GS
= 0V, V
DS
= 0V to 32V
h
MOSFET symbol
T
J
= 25°C, I
S
= 195A, V
GS
= 0V
g
integral reverse
p-n junction diode.
V
GS
= 20V
Conditions
V
GS
= 0V, I
D
= 250μA
Reference to 25°C, I
D
= 5mA
d
V
GS
= 10V, I
D
= 195A
g
V
GS
= -20V
showing
the
V
DS
= 20V
Conditions
V
GS
= 4.5V
g
V
GS
= 0V
V
DS
= 25V
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 32V
i
IRLB3034PbF
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3
Fig 1.
Typical Output Characteristics
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 2.
Typical Output Characteristics
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
1
2
3
4
5
V
GS
, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
10000
I
D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
T
J
= 25°C
T
J
= 175°C
V
DS
= 25V
≤
60μs PULSE WIDTH
-60 -40 -20
0
20 40 60 80 100120140160180
T
J
, Junction Temperature (°C)
0.5
1.0
1.5
2.0
R
D
S
(
o
n
)
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
(
N
o
r
m
a
l
i
z
e
d
)
I
D
= 195A
V
GS
= 10V
1
10
100
V
DS
, Drain-to-Source Voltage (V)
100
1000
10000
100000
C
,
C
a
p
a
c
i
t
a
n
c
e
(
p
F
)
V
GS
= 0V,
f = 1 MHZ
C
iss
= C
gs
+ C
gd
,
C
ds
SHORTED
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
C
oss
C
rss
C
iss
0
20
40
60
80
100
120
140
Q
G
,
Total Gate Charge (nC)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
G
S
,
G
a
t
e
-
t
o
-
S
o
u
r
c
e
V
o
l
t
a
g
e
(
V
)
V
DS
= 32V
V
DS
= 20V
I
D
= 185A
0.1
1
10
100
V
DS
, Drain-to-Source Voltage (V)
1
10
100
1000
10000
100000
I
D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
VGS
TOP
15V
10V
8.0V
4.5V
3.5V
3.0V
2.7V
BOTTOM
2.5V
≤
60μs PULSE WIDTH
Tj = 25°C
2.5V
0.1
1
10
100
V
DS
, Drain-to-Source Voltage (V)
10
100
1000
10000
100000
I
D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
VGS
TOP
15V
10V
8.0V
4.5V
3.5V
3.0V
2.7V
BOTTOM
2.5V
≤
60μs PULSE WIDTH
Tj = 175°C
2.5V
IRLB3034PbF
4
www.irf.com
Fig 8.
Maximum Safe Operating Area
Fig 10.
Drain-to-Source Breakdown Voltage
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 11.
Typical C
OSS
Stored Energy
Fig 9.
Maximum Drain Current vs.
Case Temperature
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
0.0
0.5
1.0
1.5
2.0
2.5
V
SD
, Source-to-Drain Voltage (V)
1.0
10
100
1000
10000
I
S
D
,
R
e
v
e
r
s
e
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
T
J
= 25°C
T
J
= 175°C
V
GS
= 0V
-60 -40 -20
0
20 40 60 80 100120140160180
T
J
, Temperature ( °C )
40
42
44
46
48
50
V
(
B
R
)
D
S
S
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
B
r
e
a
k
d
o
w
n
V
o
l
t
a
g
e
(
V
)
Id = 5mA
0
5
10
15
20
25
30
35
40
45
V
DS,
Drain-to-Source Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
E
n
e
r
g
y
(
?
J
)
25
50
75
100
125
150
175
Starting T
J
, Junction Temperature (°C)
0
200
400
600
800
1000
1200
E
A
S
,
S
i
n
g
l
e
P
u
l
s
e
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
I
D
TOP
38.9A
65.3A
BOTTOM 195A
25
50
75
100
125
150
175
T
C
, Case Temperature (°C)
0
50
100
150
200
250
300
350
I
D
,
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
Limited By Package
0.1
1
10
100
V
DS
, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
I
D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
OPERATION IN THIS AREA
LIMITED BY R
DS
(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100?sec
1msec
10msec
DC
LIMITED BY PACKAGE
IRLB3034PbF
www.irf.com
5
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14.
Typical Avalanche Current vs.Pulsewidth
Fig 15.
Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
?
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
⋅f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3⋅BV⋅I
av
) =
D
T/ Z
thJC
I
av
=
2
D
T/ [1.3⋅BV⋅Z
th
]
E
AS (AR)
= P
D (ave)
⋅t
av
25
50
75
100
125
150
175
Starting T
J
, Junction Temperature (°C)
0
50
100
150
200
250
300
E
A
R
,
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
TOP
Single Pulse
BOTTOM
1.0% Duty Cycle
I
D
= 195A
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
1
, Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
T
h
e
r
m
a
l
R
e
s
p
o
n
s
e
(
Z
t
h
J
C
)
°
C
/
W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
?
J
?
J
?
1
?
1
?
2
?
2
?
3
?
3
R
1
R
1
R
2
R
2
R
3
R
3
Ci i
/
Ri
Ci=
?
i
/
Ri
?
?
C
?
4
?
4
R
4
R
4
Ri (°C/W)
?
i (sec)
0.02477
0.000025
0.08004
0.000077
0.19057
0.001656
0.10481
0.008408
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
1
10
100
1000
A
v
a
l
a
n
c
h
e
C
u
r
r
e
n
t
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
??
j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
?
Tj = 150°C and
Tstart =25°C (Single Pulse)
IRLB3034PbF
6
www.irf.com
Fig. 17
- Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage vs. Temperature
Fig. 19
- Typical Stored Charge vs. di
f
/dt
Fig. 18
- Typical Recovery Current vs. di
f
/dt
Fig. 20
- Typical Stored Charge vs. di
f
/dt
-75 -50 -25
0
25
50
75 100 125 150 175
T
J
, Temperature ( °C )
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
G
S
(
t
h
)
,
G
a
t
e
t
h
r
e
s
h
o
l
d
V
o
l
t
a
g
e
(
V
)
I
D
= 250?A
I
D
= 1.0mA
ID = 1.0A
0
100
200
300
400
500
di
F
/dt (A/?s)
0
100
200
300
400
Q
R
R
(
A
)
I
F
= 78A
V
R
= 34V
T
J
= 25°C
T
J
= 125°C
0
100
200
300
400
500
di
F
/dt (A/?s)
0
100
200
300
400
Q
R
R
(
A
)
I
F
= 117A
V
R
= 34V
T
J
= 25°C
T
J
= 125°C
0
100
200
300
400
500
di
F
/dt (A/?s)
0
2
4
6
8
10
12
14
I
R
R
M
(
A
)
I
F
= 78A
V
R
= 34V
T
J
= 25°C
T
J
= 125°C
0
100
200
300
400
500
di
F
/dt (A/?s)
0
2
4
6
8
10
12
14
I
R
R
M
(
A
)
I
F
= 117A
V
R
= 34V
T
J
= 25°C
T
J
= 125°C
IRLB3034PbF
www.irf.com
7
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
t
p
V
(BR)DSS
I
AS
R
G
I
AS
0.01
?
t
p
D.U.T
L
V
DS
+
-
V
DD
DRIVER
A
15V
20V
V
GS
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
?
5%
Body Diode
Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
➂
➃
➁
R
G
V
DD
•
dv/dt controlled by R
G
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor "D"
•
D.U.T. - Device Under Test
D.U.T
➀
Inductor Current
D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
μ
F
50K
?
.2
μ
F
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
V
DS
Pulse Width
? 1
μs
Duty Factor
? 0.1 %
R
D
V
GS
R
G
D.U.T.
+
-
V
DD
V
GS
IRLB3034PbF
8
www.irf.com
TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
INTERNATIONAL
PART NUMBER
RECTIFIER
LOT CODE
ASSEMBLY
LOGO
YEAR 0 = 2000
DATE CODE
WEEK 19
LINE C
LOT CODE 1789
EXAMPLE:
THIS IS AN IRF1010
Note:
"P"
in assembly line position
indicates
"Lead -
Free"
IN THE ASSEMBLY LINE
"C"
ASSEMBLED ON WW 19,2000
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
.
01/09
