The Si53302 is a low jitter multi-format buffer (100 fs RMS typical), providing performance comparable to fixed-format buffers. This breakthrough performance maximizes jitter margin for other components in a clock tree design. In addition, the device’s 2:1 input mux provides more than 60 dB noise isolation between clock inputs, significantly minimizing cross-talk induced jitter and guaranteeing low noise operation in applications requiring two input clocks. On-chip supply voltage regulation provides high power supply noise rejection (PSRR), ensuring robust low-jitter operation alongside FPGAs, ASICs, SoCs and PHYs. A benefit of applying the Si53302 is the maximized jitter budget for other components, simplifying component selection and PCB design, with 40% lower jitter than competing solutions in fault-tolerant applications requiring two input clocks. The high PSRR performance provides 20 dB greater noise rejection than competing solutions, ensuring reliable low jitter operation in noisy PCB environments.